A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. - Hui-Chin Tseng; Hsin-Hung Ou; Chi-Sheng Lin; Bin-Da Liu (ISLPED, 2004)

A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. - Hsin-Hung Ou; Bin-Da Liu (ISCAS (3), 2005)

Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture. - Hsin-Hung Ou; Soon-Jyh Chang; Bin-Da Liu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture. - Hsin-Hung Ou; Bin-Da Liu; Soon-Jyh Chang (IEICE Trans. Electron., 2008)