Characterization of 1/f noise vs. number of gate stripes in MOS transistors. - Hsin-Shu Chen; A. Ito (ISCAS (2), 1999)

A 14-b 20-Msamples/s CMOS pipelined ADC. - Hsin-Shu Chen; Bang-Sup Song; Kantilal Bacrania (IEEE J. Solid State Circuits, 2001)

High-Resolution Nyquist -Rate Analog -to -Digital Converter - Hsin-Shu Chen (2001)

A 1.5-V 10-ppm/°C 2nd-order curvature-compensated CMOS bandgap reference with trimming. - Sen-Wen Hsiao; Yen-Chih Huang; David Liang; Hung-Wei Kevin Chen; Hsin-Shu Chen (ISCAS, 2006)

A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-µm CMOS. - Hung-Wei Chen; I-Ching Chen; Huan-Chieh Tseng; Hsin-Shu Chen (IEEE J. Solid State Circuits, 2009)

A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop. - Hsin-Shu Chen; Jyun-Cheng Lin (IEICE Trans. Electron., 2010)

A highly integrated class-D amplifier using driver delay hysteresis control. - Jia-Nan Tai; Hsin-Shu Chen; Hang-Quei Chiu (VLSI-DAT, 2012)

A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS. - Hung-Yen Tai; Hung-Wei Chen; Hsin-Shu Chen (VLSIC, 2012)

A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC. - Chien-Jian Tseng; Hung-Wei Chen; Wei-Ting Shen; Wei-Chih Cheng; Hsin-Shu Chen (IEEE J. Solid State Circuits, 2012)

A High-Efficiency CMOS DC-DC Converter With 9-µs Transient Recovery Time. - Pang-Jung Liu; Wei-Shan Ye; Jia-Nan Tai; Hsin-Shu Chen; Jau-Horng Chen; Yi-Jan Emery Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC. - Chien-Jian Tseng; Yi-Chun Hsieh; Ching-Hua Yang; Hsin-Shu Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS. - Yao-Sheng Hu; Chi-Huai Shih; Hung-Yen Tai; Hung-Wei Chen; Hsin-Shu Chen (A-SSCC, 2014)

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. - Hung-Yen Tai; Yao-Sheng Hu; Hung-Wei Chen; Hsin-Shu Chen (ISSCC, 2014)

A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS. - Hung-Yen Tai; Cheng-Hsueh Tsai; Pao-Yang Tsai; Hung-Wei Chen; Hsin-Shu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration. - Chien-Jian Tseng; Chieh-Fan Lai; Hsin-Shu Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC. - Yao-Sheng Hu; Po-Chao Huang; Mi-Ti Yang; Shih-Wei Wu; Hsin-Shu Chen (A-SSCC, 2016)

A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique. - Yao-Sheng Hu; Kai-Yue Lin; Hsin-Shu Chen (A-SSCC, 2016)

An 8-bit 900MS/S two-step SAR ADC. - Po-Chao Huang; Yao-Sheng Hu; Hung-Yen Tai; Hsin-Shu Chen (ISCAS, 2016)

A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC. - Yao-Sheng Hu; Po-Chao Huang; Hung-Yen Tai; Hsin-Shu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique. - Tsung-Han Tsai; Hung-Yen Tai; Pao-Yang Tsai; Cheng-Hsueh Tsai; Hsin-Shu Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A current average control method for transient-glitch reduction in variable frequency DC-DC converters. - Hsin-Shu Chen; Jia-Nan Tai; Yi-Jan Emery Chen; Jau-Horng Chen (ISCAS, 2017)

A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. - Yao-Sheng Hu; Li-Yu Huang; Hsin-Shu Chen (A-SSCC, 2018)

An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration. - Yao-Sheng Hu; Jhao-Huei Lin; Ding-Guo Lin; Kai-Yue Lin; Hsin-Shu Chen (A-SSCC, 2018)

A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting. - Kai-Ren Cheng; Hsin-Shu Chen; Mickaël Lallart; Wen-Jong Wu (ISCAS, 2018)

A Fast-Transient Switched-Capacitor DC-DC Converter with a Current Sensing Control Technique. - Chi-Wei Chen; Hsin-Shu Chen; Wen-Jong Wu (MWSCAS, 2019)

A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. - Yao-Sheng Hu; Li-Yu Huang; Hsin-Shu Chen (IEEE J. Solid State Circuits, 2019)

A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration. - Hsin-Shu Chen; Sheng-Hsiang Huang; Hung-Yen Tai; Sen-Wei Lin; Shih-Wei Wu (ISCAS, 2020)

Reconfigurable Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Frequency Scaling Techniques. - Tun-Yen Liao; Hsin-Shu Chen; Wen-Jong Wu (ISCAS, 2021)

A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC. - Chi-Wei Chen; Chien-Yu Su; Hsin-Shu Chen (ISCAS, 2022)

A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback. - Jun-Yi Wu; Hsin-Shu Chen (MWSCAS, 2023)

Pulsed-Laser-Induced Single-Event Upset in Dynamic Comparator by Incorporating Experimental Parameters Into Simulations. - Shih-Bo Yu; Chun-Hao Liang; Chien-Ping Hung; Yu-Lin Chen; Pei-Kai Liao; Jia-Han Li; Hsin-Shu Chen; Chia-Ray Chen; Chien-Kai Tseng (IEEE Trans. Instrum. Meas., 2024)

An SRAM-Based PUF with High Native-Stability Using Alternative Configuration Technique. - Sharon Isabelle Timotius; Yi-Lun Wang; Hsin-Shu Chen (ICCE, 2025)

A 94.8% Peak-Efficiency 3-Level Buck Converter with Fast Flying Capacitor Charging Technique. - Chi-Wei Chen; Jia-Yi Chen; Hsin-Shu Chen (ISCAS, 2025)