A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. - Hsin-Wen Ting; Bin-Da Liu; Soon-Jyh Chang (Asian Test Symposium, 2004)

A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. - Ruei-Jhe Tsai; Hsin-Wen Ting; Chi-Sheng Lin; Bin-Da Liu (APCCAS, 2006)

Histogram Based Testing Strategy for ADC. - Hsin-Wen Ting; Bin-Da Liu; Soon-Jyh Chang (ATS, 2006)

Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. - Hsin-Wen Ting; Cheng-Wu Lin; Bin-Da Liu; Soon-Jyh Chang (J. Electron. Test., 2007)

A Histogram-Based Testing Method for Estimating A/D Converter Performance. - Hsin-Wen Ting; Bin-Da Liu; Soon-Jyh Chang (IEEE Trans. Instrum. Meas., 2008)

A SAR ADC BIST for simplified linearity test. - An-Sheng Chao; Soon-Jyh Chang; Hsin-Wen Ting (SoCC, 2011)

Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs. - Jin-Fu Lin; Hsin-Wen Ting (J. Electron. Test., 2011)

An Output Response Analyzer Circuit for ADC Built-in Self-Test. - Hsin-Wen Ting (J. Electron. Test., 2011)

A Design of Linearity Built-in Self-Test for Current-Steering DAC. - Hsin-Wen Ting; Soon-Jyh Chang; Su-Ling Huang (J. Electron. Test., 2011)

Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images. - Hsieh-Wei Lee; King-Chu Hung; Bin-Da Liu; Sheau-Fang Lei; Hsin-Wen Ting (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction. - Jin-Fu Lin; Soon-Jyh Chang; Te-Chieh Kung; Hsin-Wen Ting; Chih-Hao Huang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Digital-Compatible Testing Scheme for Operational Amplifier. - Hsin-Wen Ting (J. Electron. Test., 2012)

A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing. - I-Jen Chao; Chung-Lun Hsu; Bin-Da Liu; Soon-Jyh Chang; Chun-Yueh Huang; Hsin-Wen Ting (IEICE Trans. Electron., 2012)

Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers. - Ren-Li Chen; Hsin-Wen Ting; Soon-Jyh Chang (IET Circuits Devices Syst., 2012)

A Low-Cost Stimulus Design for Linearity Test in SAR ADCs. - An-Sheng Chao; Cheng-Wu Lin; Hsin-Wen Ting; Soon-Jyh Chang (IEICE Trans. Electron., 2014)

A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS. - An-Sheng Chao; Cheng-Wu Lin; Hsin-Wen Ting; Soon-Jyh Chang (Int. J. Circuit Theory Appl., 2015)

Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs. - Chun-Po Huang; Hsin-Wen Ting; Soon-Jyh Chang (IEEE Trans. Instrum. Meas., 2016)

A Digital Testing Strategy for Characterizing an Analog Circuit Block. - Hsin-Wen Ting (IEEE Trans. Instrum. Meas., 2016)

Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology. - Chi-Hsien Wu; Jau-Ji Jou; Hsin-Wen Ting; Shao-I Chu; Bing-Hong Liu (ISOCC, 2017)

Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing. - I-Jen Chao; Bin-Da Liu; Soon-Jyh Chang; Chun-Yueh Huang; Hsin-Wen Ting (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs. - Yen-Long Lee; Yu-Po Cheng; Soon-Jyh Chang; Hsin-Wen Ting (IEEE Des. Test, 2018)

A VLSI On-Chip Analog High-Order Low-Pass Filter Performance Evaluation Strategy. - Hsin-Wen Ting; Chi-Yuan Chen (IEEE Trans. Instrum. Meas., 2018)