Identifying Untestable Faults in Sequential Circuits. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (IEEE Des. Test Comput., 1995)

Invalid State Identification for Sequential Circuit Test Generation. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 1996)

Identifying invalid states for sequential circuit test generation. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (VTS, 1998)

An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. - Hsing-Chung Liang; Chung-Len Lee (Asian Test Symposium, 1999)

Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. - Hsing-Chung Liang; Chung-Len Lee (J. Inf. Sci. Eng., 2000)

Identify unrepairability to speed-up spare allocation for repairing memories. - Hsing-Chung Liang; Wen-Chin Ho; Ming-Chieh Cheng (IEEE Trans. Reliab., 2005)

Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories. - Hsing-Chung Liang; Le-Quen Tzeng (MTDT, 2006)

Testing Transition Delay Faults in Modified Booth Multipliers. - Hsing-Chung Liang; Pao-Hsin Huang; Yan-Fei Tang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Improved Representatives for Judging Unrepairability and Deciding Economic Repair Solutions of Memories. - Hsing-Chung Liang (J. Circuits Syst. Comput., 2009)

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. - Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Andrew Yi-Ann Huang; Ji-Wei Li; Leon Li-Yang Chen; Nova Cheng-Yen Tsai; Sying-Jyan Wang; Chen-Shiun Lee; Leon Chou; Peter Yi-Yu Liao; Hsing-Chung Liang; Jwu E. Chen (DATE, 2020)

Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. - Katherine Shu-Min Li; Leon Li-Yang Chen; Ken Chau-Cheung Cheng; Peter Yi-Yu Liao; Sying-Jyan Wang; Andrew Yi-Ann Huang; Nova Cheng-Yen Tsai; Leon Chou; Gus Chang-Hung Han; Jwu E. Chen; Hsing-Chung Liang; Chun-Lung Hsu (ETS, 2021)

GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer. - Hua-Ren Li; Hsing-Chung Liang (ETS, 2021)

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. - Leon Li-Yang Chen; Katherine Shu-Min Li; Xu-Hao Jiang; Sying-Jyan Wang; Andrew Yi-Ann Huang; Jwu E. Chen; Hsing-Chung Liang; Chun-Lung Hsu (ITC, 2021)