Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. - Hsinwei Chou; Yu-Hao Wang; Charlie Chung-Ping Chen (ASP-DAC, 2005)

Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States. - Clayton B. McDonald; Hsinwei Chou; Vijay Durairaj; Pey-Chang Kent Lin (ICCAD, 2015)