A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. - Hsiu-Cheng Chang; Chien-Chang Lin; Jiun-In Guo (ISCAS (6), 2005)

A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. - Hsiu-Cheng Chang; Jia-Wei Chen; Ching-Lung Su; Yao-Chang Yang; Yao Li; Chun-Hao Chang; Ze-Min Chen; Wei-Sen Yang; Chien-Chang Lin; Ching-Wen Chen; Jinn-Shyan Wang; Jiun-In Guo (ISSCC, 2007)

A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. - Chun-Hao Chang; Jia-Wei Chen; Hsiu-Cheng Chang; Yao-Chang Yang; Jinn-Shyan Wang; Jiun-In Guo (SiPS, 2007)

A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. - Chien-Chang Lin; Jia-Wei Chen; Hsiu-Cheng Chang; Yao-Chang Yang; Yi-Huan Ou-Yang; Ming-Chih Tsai; Jiun-In Guo; Jinn-Shyan Wang (IEEE J. Solid State Circuits, 2007)

A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding. - Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (APCCAS, 2008)

A dynamic quality-scalable H.264 video encoder chip. - Hsiu-Cheng Chang; Yao-Chang Yang; Jia-Wei Chen; Ching-Lung Su; Cheng-An Chien; Jiun-In Guo; Jinn-Shyan Wang (ASP-DAC, 2009)

A Dynamic Quality-scalable H.264 Video Encoder. - Hsiu-Cheng Chang; Jia-Wei Chen; Yao-Chang Yang; Cheng-An Chien; Tzu-Chun Chang; Jinn-Shyan Wang; Jiun-In Guo (ISCAS, 2009)

A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards. - Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (ISCAS, 2009)

A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications. - Hsiu-Cheng Chang; Jia-Wei Chen; Bing-Tsung Wu; Ching-Lung Su; Jinn-Shyan Wang; Jiun-In Guo (IEEE Trans. Circuits Syst. Video Technol., 2009)

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. - Cheng-An Chien; Yao-Chang Yang; Hsiu-Cheng Chang; Jia-Wei Chen; Cheng-Yen Chang; Jiun-In Guo; Jinn-Shyan Wang; Ching-Hwa Cheng (ASP-DAC, 2011)

A dynamic quality-adjustable H.264 intra coder. - Jia-Wei Chen; Hsiu-Cheng Chang; Jinn-Shyan Wang; Jiun-In Guo (IEEE Trans. Consumer Electron., 2011)

An inter-frame/inter-view cache architecture design for multi-view video decoders. - Jui-Sheng Lee; Sheng-Han Wang; Chih-Tai Chou; Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (APSIPA, 2012)

A two level mode decision algorithm for H.264 high profile intra encoding. - Cheng-Yen Chang; Cheng-An Chien; Hsiu-Cheng Chang; Jia-Wei Chen; Jiun-In Guo (ISCAS, 2012)

High efficiency data access system architecture for deblocking filter supporting multiple video coding standards. - Cheng-An Chien; Guo-An Jian; Hsiu-Cheng Chang; Kuan-Hung Chen; Jiun-In Guo (IEEE Trans. Consumer Electron., 2012)

A view scalable multi-view video decoder system. - Jui-Sheng Lee; Yuan-Hsiang Miao; Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (VLSI-DAT, 2013)

An Adaboost-based two-level moving object detection architecture with dynamic ROI allocation. - Jui-Sheng Lee; Hsiu-Cheng Chang; Jiun-In Guo (ICCE-TW, 2014)

A 360-degree panoramic video system design. - Kai-Chen Huang; Po-Yu Chien; Cheng-An Chien; Hsiu-Cheng Chang; Jiun-In Guo (VLSI-DAT, 2014)