Recent research development in flip-chip routing. - Hsu-Chieh Lee; Yao-Wen Chang; Po-Wei Lee (ICCAD, 2010)

High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. - Xin-Wei Shih; Hsu-Chieh Lee; Kuan-Hsien Ho; Yao-Wen Chang (ICCAD, 2010)

A chip-package-board co-design methodology. - Hsu-Chieh Lee; Yao-Wen Chang (DAC, 2012)

Obstacle-avoiding free-assignment routing for flip-chip designs. - Po-Wei Lee; Hsu-Chieh Lee; Yuan-Kai Ho; Yao-Wen Chang; Chen-Feng Chang; I-Jye Lin; Chin-Fang Shen (DAC, 2012)

Symmetrical buffered clock-tree synthesis with supply-voltage alignment. - Xin-Wei Shih; Tzu-Hsuan Hsu; Hsu-Chieh Lee; Yao-Wen Chang; Kai-Yuan Chao (ASP-DAC, 2013)

Escape Routing for Staggered-Pin-Array PCBs. - Yuan-Kai Ho; Hsu-Chieh Lee; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs. - Yuan-Kai Ho; Hsu-Chieh Lee; Webber Lee; Yao-Wen Chang; Chen-Feng Chang; I-Jye Lin; Chin-Fang Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)