An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. - Hsu-Kang Dow; Ching-Hua Huang; Chun-Hung Lai; Kai-Hsiang Tsao; Sheng-Chih Tseng; Kun-Yi Wu; Ting-Hsuan Wu; Ho-Chun Yang; Da-Jing Zhang-Jian; Yun-Nan Chang; Steve Haga; Shen-Fu Hsiao; et al. (VLSI-DAT, 2015)

A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory. - Ing-Jer Huang; Chun-Hung Lai; Yun-Chung Yang; Hsu-Kang Dow; Hung-Lun Chen (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Bio-Sensing System-on-Chip and Software for Smart Clothes. - Hsu-Kang Dow; Ing-Jer Huang; Robert Rieger; Ko-Chi Kuo; Lan-Yuen Guo; Shih-Jung Pao (ICCE, 2019)

SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. - Hsu-Kang Dow; Tuo Li 001; William Miles; Sri Parameswaran (DAC, 2021)

HWST128: complete memory safety accelerator on RISC-V with metadata compression. - Hsu-Kang Dow; Tuo Li 001; Sri Parameswaran (DAC, 2022)