3D Test Wrapper Chain Optimization with I/O Cells Binding Considered. - Fan-Hsuan Tang; Hsu-Yu Kao; Shih-Hsu Huang; Jin-Fu Li 001 (3DIC, 2019)

Hardware Implementation for Multiple Activation Functions. - Chih-Hsiang Chang; Hsu-Yu Kao; Shih-Hsu Huang (ICCE-TW, 2019)

A Design Framework for Hardware Approximation of Deep Neural Networks. - Wei-Hung Lin; Hsu-Yu Kao; Shih-Hsu Huang (ISPACS, 2019)

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. - Jui-Hung Hung; Shih-Hsu Huang; Chun-Hua Cheng; Hsu-Yu Kao; Wei-Kai Cheng (VTS, 2020)

Block-Based Compression for Reducing Indexing Cost of DNN Accelerators. - Yui-Kai Weng; Shih-Hsu Huang; Hsu-Yu Kao (ICCE-TW, 2021)

Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators. - Wei-Hung Lin; Hsu-Yu Kao; Shih-Hsu Huang (ISOCC, 2021)

Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing. - Hsu-Yu Kao; Xin-Jia Chen; Shih-Hsu Huang (Sensors, 2021)

Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations. - Yui-Kai Weng; Shih-Hsu Huang; Hsu-Yu Kao (Sensors, 2021)

A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations. - Hsu-Yu Kao; Shih-Hsu Huang (AICAS, 2022)

A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration. - Bo-Xi Lai; Shih-Hsu Huang; Hsu-Yu Kao (ICCE-TW, 2022)