Feasible two-way circuit partitioning with complex resource constraints. - Hsun-Cheng Lee; Ting-Chi Wang (ASP-DAC, 2000)

Multilevel floorplanning/placement for large-scale modules using B*-trees. - Hsun-Cheng Lee; Yao-Wen Chang; Jer-Ming Hsu; Hannah Honghua Yang (DAC, 2003)

MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. - Hsun-Cheng Lee; Yao-Wen Chang; Hannah Honghua Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

An innovative scheme for the UNI interworking of ASON and GMPLS. - Chin-Cheng Hu; Chin-Wei Lin; Hsun-Cheng Lee; Ching-Sheu Wang (WOCC, 2012)

A novel low power 11-bit hybrid ADC using flash and delay line architectures. - Hsun-Cheng Lee; Jacob A. Abraham (DATE, 2014)

Harmonic distortion correction for 8-bit delay line ADC using gray code. - Hsun-Cheng Lee; Jacob A. Abraham (LATW, 2014)

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction. - Hsun-Cheng Lee; Jacob A. Abraham (J. Electron. Test., 2015)