A new register file access architecture for software pipelining in VLIW processors. - Yanjun Zhang; Hu He 001; Yihe Sun (ASP-DAC, 2005)

VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design. - Zheng Shen; Hu He 001; Yanjun Zhang; Yihe Sun (IIH-MSP, 2006)

A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. - Zhixiong Zhou; Hu He 001; Yanjun Zhang; Yihe Sun; Adriel Cheng (ASAP, 2007)

Heuristic on a Novel Power Management System Cooperating with Compiler. - Yang Xu; Hu He 001; Zhou Zhixiong; Yanjun Zhang; Yihe Sun (J. Low Power Electron., 2007)

A Video Specific Instruction Set Architecture for ASIP design. - Zheng Shen; Hu He 001; Yanjun Zhang; Yihe Sun (VLSI Design, 2007)

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. - Adriel Cheng; Cheng-Chew Lim; Yihe Sun; Hu He 001; Zhixiong Zhou; Ting Lei (DELTA, 2008)

Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. - Zheng Shen; Hu He 001; Yihe Sun (DSD, 2009)

A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures. - Yang Xu; Hu He 001; Yihe Sun (J. Low Power Electron., 2009)

A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). - Jianfeng Zhu 001; Dong Wu; Yaru Yan; Xiao Yu; Hu He 001; Liyang Pan (FPGA, 2011)

A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect. - Jianfeng Zhu 001; Hu He 001; Dong Wu; Liyang Pan (J. Electron. Test., 2011)

Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect. - Jianfeng Zhu 001; Hu He 001; Dong Wu; Liyang Pan (J. Electron. Test., 2011)

An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems. - Xu Yang 003; Hu He 001 (Sensors, 2012)

Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems. - Xu Yang 003; Yanjun Zhang; Dake Liu; Deyuan Guo; Hu He 001 (IET Wirel. Sens. Syst., 2013)

An Implementation of Message-Passing Interface over VxWorks for Real-Time Embedded Multi-Core Systems. - Xu Yang 003; Deyuan Guo; Hu He 001; Haijing Tang; Yanjun Zhang (Comput. J., 2014)

A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA. - Jianfeng Zhu 001; Liyang Pan; Yaru Yan; Dong Wu; Hu He 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW. - Yumin Hou; Hu He 001; Xu Yang 003; Deyuan Guo; Xu Wang; Jiawei Fu; Keni Qiu (VLSI Design, 2016)

On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage. - Hu He 001; Xu Yang 003; Yanjun Zhang (Comput. J., 2017)

R2D2: Runtime reassurance and detection of A2 Trojan. - Yumin Hou; Hu He 001; Kaveh Shamsi; Yier Jin; Dong Wu; Huaqiang Wu (HOST, 2018)

Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. - Wenqiang Zhang; Xiaochen Peng; Huaqiang Wu; Bin Gao 006; Hu He 001; Youhui Zhang; Shimeng Yu; He Qian (DAC, 2019)

Exploration of a mechanism to form bionic, self-growing and self-organizing neural network. - Xu Yang 003; Guo Liu; Songgaojun Deng; Zichao Wei; Hu He 001; Yingjie Shang; Ning Deng 008 (Artif. Intell. Rev., 2019)

Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods. - Yumin Hou; Xu Wang; Jiawei Fu; Junping Ma; Hu He 001; Xu Yang 003 (J. Circuits Syst. Comput., 2019)

A Processing-in-Memory Architecture Programming Paradigm for Wireless Internet-of-Things Applications. - Xu Yang 003; Yumin Hou; Hu He 001 (Sensors, 2019)

CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things. - Xu Yang 003; Yumin Hou; Junping Ma; Hu He 001 (Sensors, 2019)

On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness. - Yumin Hou; Hu He 001; Kaveh Shamsi; Yier Jin; Dong Wu; Huaqiang Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

The Algorithm of Spiking Neural Network And Application in Poker Games. - Liya Dong; Qilin Wang; Hu He 001 (ICMSSP, 2020)

HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU. - Yanhai Jiang; Bin Gao 006; Jianshi Tang; Dabin Wu; Hu He 001; He Qian; Huaqiang Wu (ICTA, 2021)

A memory neural system built based on spiking neural network. - Hu He 001; Qilin Wang; Xu Yang 003; Yunlin Lei; Jia Cai; Ning Deng 008 (Neurocomputing, 2021)

ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing. - Hanwen Gong; Hu He 001; Bin Gao 006; Jianshi Tang; Qingtian Zhang; He Qian; Huaqiang Wu (ICTA, 2023)

A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit. - Hanwen Gong; Hu He 001; Bin Gao 006; Jianshi Tang; Jian Yu; Dabin Wu; Junren Chen; Qingtian Zhang; Xing Mou; He Qian; Huaqiang Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system. - Ruihua Yu; Wenqiang Zhang; Bin Gao 006; Yiwen Geng; Peng Yao; Yuyi Liu; Qingtian Zhang; Jianshi Tang; Dong Wu; Hu He 001; Ning Deng 008; He Qian; et al. (Sci. China Inf. Sci., 2023)

An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration. - Hanwen Gong; Hu He 001; Liyang Pan; Bin Gao 006; Jianshi Tang; Sining Pan; Jianing Li; Peng Yao; Dabin Wu; He Qian; Huaqiang Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

HCRF: A Hardware Checkpoint-based Recovery Framework in light dual-core lockstep processors. - Jingzhou Li; Huaiyu Chen; Wenbin Zhang; Hu He 001 (ACM Great Lakes Symposium on VLSI, 2024)

Ventus: A High-performance Open-source GPGPU Based on RISC-V and Its Vector Extension. - Jingzhou Li; Kexiang Yang; Chufeng Jin; Xudong Liu; Zexia Yang; Fangfei Yu; Yujie Shi; Mingyuan Ma; Li Kong; Jing Zhou; Hualin Wu; Hu He 001 (ICCD, 2024)

RISC-V-Based GPGPU With Vector Capabilities for High-Performance Computing. - Jingzhou Li; Fangfei Yu; Mingyuan Ma; Wei Liu; Yuhan Wang; Hualin Wu; Hu He 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)