Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits. - Hu Xu 002; Vasilis F. Pavlidis; Giovanni De Micheli (NanoNet, 2009)

Synchronization and power integrity issues in 3-D ICs. - Vasilis F. Pavlidis; Hu Xu 002; Ioannis Tsioutsios; Giovanni De Micheli (APCCAS, 2010)

Process-induced skew variation for scaled 2-D and 3-D ICs. - Hu Xu 002; Vasilis F. Pavlidis; Giovanni De Micheli (SLIP, 2010)

Analytical heat transfer model for thermal through-silicon vias. - Hu Xu 002; Vasilis F. Pavlidis; Giovanni De Micheli (DATE, 2011)

Skew variability in 3-D ICs with multiple clock domains. - Hu Xu 002; Vasilis F. Pavlidis; Giovanni De Micheli (ISCAS, 2011)

Enhanced wafer matching heuristics for 3-D ICs. - Vasilis F. Pavlidis; Hu Xu 002; Giovanni De Micheli (ETS, 2012)

The combined effect of process variations and power supply noise on clock skew and jitter. - Hu Xu 002; Vasilis F. Pavlidis; Wayne P. Burleson; Giovanni De Micheli (ISQED, 2012)

Effect of process variations in 3D global clock distribution networks. - Hu Xu 002; Vasilis F. Pavlidis; Giovanni De Micheli (ACM J. Emerg. Technol. Comput. Syst., 2012)

Modeling and Design Techniques for 3-D ICs under Process, Voltage, and Temperature Variations. - Hu Xu 002 (2012)

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise. - Hu Xu 002; Vasilis F. Pavlidis; Xifan Tang; Wayne P. Burleson; Giovanni De Micheli (IEEE Trans. Very Large Scale Integr. Syst., 2013)