Teaching three-dimensional system-in-package design automation in a semester course. - Shih-Hsu Huang; Wen-Pin Tu; Hua-Hsin Yeh; Chun-Hua Cheng (MSE, 2011)

A formal approach to slack-driven high-level synthesis. - Hua-Hsin Yeh; Shih-Hsu Huang; Chun-Hua Cheng (ISCAS, 2012)

Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol. - Hua-Hsin Yeh; Wen-Pin Tu; Jian-Zhi Shen; Tung-Hua Yen; Shih-Hsu Huang (APCCAS, 2014)

Live demonstration: A low-power high-level synthesis system. - Hua-Hsin Yeh; Chun-Hua Cheng; Shih-Hsu Huang (APCCAS, 2014)

Leakage-power-aware clock period minimization. - Hua-Hsin Yeh; Shih-Hsu Huang; Yow-Tyng Nieh (DATE, 2014)

Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits. - Shih-Hsu Huang; Hua-Hsin Yeh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Clock Period Minimization with Minimum Leakage Power. - Shih-Hsu Huang; Hua-Hsin Yeh; Yow-Tyng Nieh (ACM Trans. Design Autom. Electr. Syst., 2015)

Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. - Chung-Han Chou; Hua-Hsin Yeh; Shih-Hsu Huang; Yow-Tyng Nieh; Shih-Chieh Chang; Yung-Tai Chang (IEEE Trans. Very Large Scale Integr. Syst., 2016)