A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. - Xiaoping Tang; Ruiqi Tian; Hua Xiang 001; D. F. Wong 001 (ICCAD, 2001)

An Algorithm for Simultaneous Pin Assignment and Routing. - Hua Xiang 001; Xiaoping Tang; D. F. Wong 001 (ICCAD, 2001)

An algorithm for integrated pin assignment and buffer planning. - Hua Xiang 001; D. F. Wong 001; Xiaoping Tang (DAC, 2002)

A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. - Li-Da Huang; Xiaoping Tang; Hua Xiang 001; D. F. Wong 001; I-Min Liu (DATE, 2002)

ECO algorithms for removing overlaps between power rails and signal wires. - Hua Xiang 001; Kai-Yuan Chao; D. F. Wong 001 (ICCAD, 2002)

Wire type assignment for FPGA routing. - Seokjin Lee; Hua Xiang 001; D. F. Wong 001; Richard Y. Sun (FPGA, 2003)

Bus-Driven Floorplanning. - Hua Xiang 001; Xiaoping Tang; Martin D. F. Wong (ICCAD, 2003)

Min-cost flow-based algorithm for simultaneous pin assignment and routing. - Hua Xiang 001; Xiaoping Tang; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

An ECO algorithm for eliminating crosstalk violations. - Hua Xiang 001; Kai-Yuan Chao; D. F. Wong 001 (ISPD, 2004)

A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. - Li-Da Huang; Xiaoping Tang; Hua Xiang 001; Martin D. F. Wong; I-Min Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

New Strategies for High Performance VLSI Physical Design - Hua Xiang 001 (2004)

Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. - Hua Xiang 001; Kai-Yuan Chao; Martin D. F. Wong (ISQED, 2005)

Wire Planning with Bounded Over-the-Block Wires. - Hua Xiang 001; I-Min Liu; Martin D. F. Wong (ISQED, 2005)

Wire density driven global routing for CMP variation and timing. - Minsik Cho; David Z. Pan; Hua Xiang 001; Ruchir Puri (ICCAD, 2006)

An ECO routing algorithm for eliminating coupling-capacitance violations. - Hua Xiang 001; Kai-Yuan Chao; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Coupling-aware Dummy Metal Insertion for Lithography. - Liang Deng; Martin D. F. Wong; Kai-Yuan Chao; Hua Xiang 001 (ASP-DAC, 2007)

TROY: Track Router with Yield-driven Wire Planning. - Minsik Cho; Hua Xiang 001; Ruchir Puri; David Z. Pan (DAC, 2007)

Is your layout density verification exact?: a fast exact algorithm for density calculation. - Hua Xiang 001; Kai-Yuan Chao; Ruchir Puri; Martin D. F. Wong (ISPD, 2007)

Dummy fill density analysis with coupling constraints. - Hua Xiang 001; Liang Deng; Ruchir Puri; Kai-Yuan Chao; Martin D. F. Wong (ISPD, 2007)

OPC-Friendly Bus Driven Floorplanning. - Hua Xiang 001; Liang Deng; Li-Da Huang; Martin D. F. Wong (ISQED, 2007)

Track Routing and Optimization for Yield. - Minsik Cho; Hua Xiang 001; Ruchir Puri; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. - Hua Xiang 001; Kai-Yuan Chao; Ruchir Puri; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Fast Dummy-Fill Density Analysis With Coupling Constraints. - Hua Xiang 001; Liang Deng; Ruchir Puri; Kai-Yuan Chao; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

History-based VLSI legalization using network flow. - Minsik Cho; Haoxing Ren; Hua Xiang 001; Ruchir Puri (DAC, 2010)

Logical and physical restructuring of fan-in trees. - Hua Xiang 001; Haoxing Ren; Louise Trevillyan; Lakshmi N. Reddy; Ruchir Puri; Minsik Cho (ISPD, 2010)

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs. - Minsik Cho; Hua Xiang 001; Haoxing Ren; Matthew M. Ziegler; Ruchir Puri (ICCAD, 2013)

Depth controlled symmetric function fanin tree restructure. - Hua Xiang 001; Lakshmi N. Reddy; Louise Trevillyan; Ruchir Puri (ICCAD, 2013)

Network flow based datapath bit slicing. - Hua Xiang 001; Minsik Cho; Haoxing Ren; Matthew M. Ziegler; Ruchir Puri (ISPD, 2013)

Row Based Dual-VDD Island Generation and Placement. - Hua Xiang 001; Haifeng Qian; Ching Zhou; Yu-Shiang Lin; Fanchieh Yee; Andrew Sullivan; Pong-Fei Lu (DAC, 2014)

Gate movement for timing improvement on row based Dual-VDD designs. - Hua Xiang 001; Lakshmi N. Reddy; Haifeng Qian; Ching Zhou; Yu-Shiang Lin; Fanchieh Yee; Andrew Sullivan; Pong-Fei Lu (ISQED, 2016)

Self-Aligned Double-Patterning Aware Legalization. - Hua Xiang 001; Gi-Joon Nam; Gustavo E. Téllez; Shyam Ramji; Xiaoqing Xu (DATE, 2020)

Routing-Free Crosstalk Prediction. - Rongjian Liang; Zhiyao Xie; Jinwook Jung; Vishnavi Chauha; Yiran Chen 001; Jiang Hu; Hua Xiang 001; Gi-Joon Nam (ICCAD, 2020)

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. - Rongjian Liang; Hua Xiang 001; Diwesh Pandey; Lakshmi N. Reddy; Shyam Ramji; Gi-Joon Nam; Jiang Hu (ISPD, 2020)

FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer. - Rongjian Liang; Jinwook Jung; Hua Xiang 001; Lakshmi N. Reddy; Alexey Lvov; Jiang Hu; Gi-Joon Nam (ICCAD, 2021)

A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions. - Rongjian Liang; Hua Xiang 001; Jinwook Jung; Jiang Hu; Gi-Joon Nam (ICCAD, 2022)

Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks. - Rongjian Liang; Hua Xiang 001; Diwesh Pandey; Lakshmi N. Reddy; Shyam Ramji; Gi-Joon Nam; Jiang Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops. - Chunkai Fu; Ben Trombley; Hua Xiang 001; Gi-Joon Nam; Jiang Hu (ISVLSI, 2023)