Matching-based minimum-cost spare cell selection for design changes. - Iris Hui-Ru Jiang; Hua-Yu Chang; Liang-Gi Chang; Huang-Bi Hung (DAC, 2009)

Live Demo: ECOS 1.0: A metal-only ECO synthesizer. - Iris Hui-Ru Jiang; Hua-Yu Chang (ISCAS, 2010)

Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. - Iris Hui-Ru Jiang; Hua-Yu Chang; Chih-Long Chang (ISPD, 2010)

Simultaneous functional and timing ECO. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (DAC, 2011)

Timing ECO optimization using metal-configurable gate-array spare cells. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (DAC, 2012)

Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

ECOS: Stable Matching Based Metal-Only ECO Synthesis. - Iris Hui-Ru Jiang; Hua-Yu Chang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

WiT: Optimal Wiring Topology for Electromigration Avoidance. - Iris Hui-Ru Jiang; Hua-Yu Chang; Chih-Long Chang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Functional ECO Using Metal-Configurable Gate-Array Spare Cells. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (DAC, 2014)

Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. - Iris Hui-Ru Jiang; Gi-Joon Nam; Hua-Yu Chang; Sani R. Nassif; Jerry Hayes (ICCAD, 2014)

Feature detection for image analytics via FPGA acceleration. - Hua-Yu Chang; Iris Hui-Ru Jiang; H. Peter Hofstee; Damir A. Jamsek; Gi-Joon Nam (IBM J. Res. Dev., 2015)

Multiple patterning layout decomposition considering complex coloring rules. - Hua-Yu Chang; Iris Hui-Ru Jiang (DAC, 2016)

Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing. - Iris Hui-Ru Jiang; Hua-Yu Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Recent Research and Challenges in Multiple Patterning Layout Decomposition. - Iris Hui-Ru Jiang; Hua-Yu Chang (ISVLSI, 2018)

Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement. - Hua-Yu Chang; Iris Hui-Ru Jiang (ISPD, 2019)

Challenges for Automating Package Routing. - Wen-Hao Liu 001; Bing Chen; Hua-Yu Chang; Gary Lin; Zi-Shen Lin (ISPD, 2022)

Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. - Yu-Yang Chen; Yi-Chen Lin; Tzu-Han Hsu; Iris Hui-Ru Jiang; Tung-Chieh Chen; Tai-Chen Chen; Hua-Yu Chang (ICCAD, 2024)