A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique. - Xiang Zheng; Ming Liu 015; Hong Chen 002; Huamin Cao; Cong Wang; Zhiqiang Gao (DDECS, 2012)

Word line interference based data recovery technique for 3D NAND Flash. - Liu Yang; Fei Liu; Huamin Cao; Qi Wang 041; Zongliang Huo (IEICE Electron. Express, 2018)