A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. - Yi-Wei Lin; Hao-I Yang; Geng-Cing Lin; Chi-Shin Chang; Ching-Te Chuang; Wei Hwang; Chia-Cheng Chen; Willis Shih; Huan-Shun Huang (ISLPED, 2012)

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. - Ming-Hsien Tu; Jihi-Yu Lin; Ming-Chien Tsai; Chien-Yu Lu; Yuh-Jiun Lin; Meng-Hsueh Wang; Huan-Shun Huang; Kuen-Di Lee; Wei-Chiang Shih; Shyh-Jye Jou; Ching-Te Chuang (IEEE J. Solid State Circuits, 2012)

A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. - Chien-Yu Lu; Ming-Hsien Tu; Hao-I Yang; Ya-Ping Wu; Huan-Shun Huang; Yuh-Jiun Lin; Kuen-Di Lee; Yung-Shin Kao; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. - Chi-Shin Chang; Hao-I Yang; Wei-Nan Liao; Yi-Wei Lin; Nan-Chun Lien; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming-Hsien Tu; Huan-Shun Huang; Yong-Jyun Hu; et al. (ISCAS, 2013)

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. - Wei-Nan Liao; Nan-Chun Lien; Chi-Shin Chang; Li-Wei Chu; Hao-I Yang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Ming-Hsien Tu; Huan-Shun Huang; Jian-Hao Wang; Paul-Sen Kan; et al. (SoCC, 2013)

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. - Chao-Kuei Chung; Chien-Yu Lu; Zhi-Hao Chang; Shyh-Jye Jou; Ching-Te Chuang; Ming-Hsien Tu; Yu-Hsian Chen; Yong-Jyun Hu; Paul-Sen Kan; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao (SoCC, 2014)

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. - Chien-Yu Lu; Ching-Te Chuang; Shyh-Jye Jou; Ming-Hsien Tu; Ya-Ping Wu; Chung-Ping Huang; Paul-Sen Kan; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line. - Shang-Lin Wu; Chien-Yu Lu; Ming-Hsien Tu; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao; Ching-Te Chuang (Microelectron. J., 2016)

A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. - Shang-Lin Wu; Kuang-Yu Li; Po-Tsang Huang; Wei Hwang; Ming-Hsien Tu; Sheng-Chi Lung; Wei-Sheng Peng; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)