Implementation and Area Optimization of LUT6 Based Convolution Structure on FPGA. - Huangtao Wu; Wenjin Huang; Rui Chen; Yihua Huang 005 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

A Tag Based Random Order Vector Reduction Circuit. - Yihua Huang 005; Wenjin Huang; Rui Chen; Huangtao Wu; Ming Wei (IEEE Access, 2020)

FPGA-Based High-Throughput CNN Hardware Accelerator With High Computing Resource Utilization Ratio. - Wenjin Huang; Huangtao Wu; Qingkun Chen; Conghui Luo; Shihao Zeng; Tianrui Li 005; Yihua Huang 005 (IEEE Trans. Neural Networks Learn. Syst., 2022)