Delay Testing with Double Observations. - Huawei Li 001; Zhongcheng Li; Yinghua Min (Asian Test Symposium, 1998)

Reduction of Number of Paths to be Tested in Delay Testing. - Huawei Li 001; Zhongcheng Li; Yinghua Min (J. Electron. Test., 2000)

An RT-Level ATPG Based on Clustering of Circuit States. - Huawei Li 001; Yinghua Min; Zhongcheng Li (Asian Test Symposium, 2001)

Reducing Power Dissipation during At-Speed Test Application. - Xiaowei Li 001; Huawei Li 001; Yinghua Min (DFT, 2001)

Test Power Optimization Techniques for CMOS Circuits. - Zuying Luo; Xiaowei Li 001; Huawei Li 001; Shiyuan Yang; Yinghua Min (Asian Test Symposium, 2002)

Clustering of behavioral phases in FSMs and its applications to VLSI test. - Huawei Li 001; Yinghua Min; Zhongcheng Li (Sci. China Ser. F Inf. Sci., 2002)

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. - Yinhe Han 001; Yongjun Xu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Asian Test Symposium, 2003)

Delay Test Pattern Generation Considering Crosstalk-Induced Effects. - Huawei Li 001; Yue Zhang; Xiaowei Li 001 (Asian Test Symposium, 2003)

A Novel RT-Level Behavioral Description Based ATPG Method. - Zhigang Yin; Yinghua Min; Xiaowei Li 001; Huawei Li 001 (J. Comput. Sci. Technol., 2003)

Rapid and Energy-Efficient Testing for Embedded Cores. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Asian Test Symposium, 2004)

Pair Balance-Based Test Scheduling for SOCs. - Yu Hu 001; Yinhe Han 001; Huawei Li 001; Tao Lv 001; Xiaowei Li 001 (Asian Test Symposium, 2004)

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (DFT, 2004)

Design of an efficient memory subsystem for network processor. - Shuguang Gong; Huawei Li 001; Yufeng Xu; Tong Liu; Xiaowei Li 001 (ASP-DAC, 2005)

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2005)

Non-robust Test Generation for Crosstalk-Induced Delay Faults. - Pei-Fu Shen; Huawei Li 001; Yong-Jun Xu 001; Xiaowei Li 001 (Asian Test Symposium, 2005)

Using MUXs Network to Hide Bunches of Scan Chains. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (ISQED, 2005)

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. - Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Xiaoqing Wen (PRDC, 2005)

Selection of Crosstalk-Induced Faults in Enhanced Delay Test. - Huawei Li 001; Xiaowei Li 001 (J. Electron. Test., 2005)

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. - Yinhe Han 001; Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2005)

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. - Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (J. Comput. Sci. Technol., 2005)

An innovative free memory design for network processors in home network gateway. - Shuguang Gong; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Consumer Electron., 2005)

Test data compression based on clustered random access scan. - Yu Hu 001; Cheng Li; Jia Li 022; Yinhe Han 001; Xiaowei Li 001; Wei Wang; Huawei Li 001; Laung-Terng Wang; Xiaoqing Wen (ATS, 2006)

An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains. - Tao Lv 001; Ling-Yi Liu; Yang Zhao; Huawei Li 001; Xiaowei Li 001 (ATS, 2006)

Fast Packet Classification using Group Bit Vector. - Tong Liu; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (GLOBECOM, 2006)

Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. - Huawei Li 001; Pei-Fu Shen; Xiaowei Li 001 (VTS, 2006)

Response compaction for system-on-a-chip based on advanced convolutional codes. - Yinhe Han 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Sci. China Ser. F Inf. Sci., 2006)

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. - Yu Hu 001; Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2006)

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. - Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (IEEE Trans. Instrum. Meas., 2006)

A Routing Algorithm for Random Error Tolerance in Network-on-Chip. - Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (HCI (4), 2007)

Bug analysis and corresponding error models in real designs. - Tao Lv 001; Tong Xu; Yang Zhao; Huawei Li 001; Xiaowei Li 001 (HLDVT, 2007)

The design-for-testability features of a general purpose microprocessor. - Da Wang; Xiaoxin Fan; Xiang Fu 007; Hui Liu; Ke Wen; Rui Li; Huawei Li 001; Yu Hu 001; Xiaowei Li 001 (ITC, 2007)

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. - Yinhe Han 001; Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Robust test generation for power supply noise induced path delay faults. - Xiang Fu 007; Huawei Li 001; Yu Hu 001; Xiaowei Li 001 (ASP-DAC, 2008)

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. - Fei Wang; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2008)

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (ATS, 2008)

A Scan-Based Delay Test Method for Reduction of Overtesting. - Hui Liu; Huawei Li 001; Yu Hu 001; Xiaowei Li 001 (DELTA, 2008)

A Case Study on At-Speed Testing for a Gigahertz Microprocessor. - Da Wang; Rui Li; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (DELTA, 2008)

Static Crosstalk Noise Analysis with Transition Map. - Minjin Zhang; Huawei Li 001; Xiaowei Li 001 (DELTA, 2008)

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. - Fei Wang; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Jing Ye 001; Yu Huang 005 (ITC, 2008)

Multiple Coupling Effects Oriented Path Delay Test Generation. - Minjin Zhang; Huawei Li 001; Xiaowei Li 001 (VTS, 2008)

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001; Yu Hu 001 (VTS, 2008)

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. - Da Wang; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2008)

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. - Song Jin; Yinhe Han 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001; Guihai Yan (Asian Test Symposium, 2009)

A Low Overhead On-Chip Path Delay Measurement Circuit. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2009)

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. - Zichu Qi; Hui Liu; Xiangku Li; Da Wang; Yinhe Han 001; Huawei Li 001; Weiwu Hu (Asian Test Symposium, 2009)

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (PRDC, 2009)

Small Delay Fault Simulation for Sequential Circuits. - Li Liu; Jishun Kuang; Huawei Li 001 (PRDC, 2009)

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (PRDC, 2009)

Impact of Hazards on Pattern Selection for Small Delay Defects. - Jie Wang; Huawei Li 001; Yinghua Min; Xiaowei Li 001; Huaguo Liang (PRDC, 2009)

Automatic Selection of Internal Observation Signals for Design Verification. - Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2009)

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2009)

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. - Lei Zhang 008; Yinhe Han 001; Qiang Xu 001; Xiaowei Li 001; Huawei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Graph partition based path selection for testing of small delay defects. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2010)

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing. - Xiang Fu 007; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. - Song Jin; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

Software-Based Self-Testing of Processors Using Expanded Instructions. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2010)

An on-chip clock generation scheme for faster-than-at-speed delay testing. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (DATE, 2010)

On generation of a universal path candidate set containing testable long paths. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (ITC, 2010)

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. - Huawei Li 001; Dawen Xu 002; Yinhe Han 001; Kwang-Ting Cheng; Xiaowei Li 001 (ITC, 2010)

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (PRDC, 2010)

Fast path selection for testing of small delay defects considering path correlations. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2010)

Testable Critical Path Selection Considering Process Variation. - Xiang Fu 007; Huawei Li 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2010)

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications. - Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2011)

Flex memory: Exploiting and managing abundant off-chip optical bandwidth. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2011)

An abacus turn model for time/space-efficient reconfigurable routing. - Binzhang Fu; Yinhe Han 001; Jun Ma; Huawei Li 001; Xiaowei Li 001 (ISCA, 2011)

A unified test architecture for on-line and off-line delay fault detections. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (VTS, 2011)

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2011)

Statistical lifetime reliability optimization considering joint effect of process variation and aging. - Song Jin; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2011)

Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. - Minjin Zhang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects. - Ying Zhang 040; Huawei Li 001; Yinghua Min; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write. - Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2012)

Statistical SDFC: A metric for evaluating test quality of small delay faults. - Xuefeng Zhu; Huawei Li 001; Xiaowei Li 001 (VLSI-DAT, 2012)

Testable Path Selection and Grouping for Faster Than At-Speed Testing. - Xiang Fu 007; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A High-Precision On-Chip Path Delay Measurement Architecture. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Path Constraint Solving Based Test Generation for Hard-to-Reach States. - Yanhong Zhou; Tiancheng Wang; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2013)

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. - Yinhe Han 001; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ISCAS, 2013)

RSAK: Random stream attack for phase change memory in video applications. - Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (VTS, 2013)

Test Path Selection for Capturing Delay Failures Under Statistical Timing Model. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. - Song Jin; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

An On-Line Timing Error Detection Method for Silicon Debug. - Yun Cheng; Huawei Li 001; Xiaowei Li 001 (ATS, 2014)

A low power DRAM refresh control scheme for 3D memory cube. - Ying Wang 001; Yinhe Han 001; Huawei Li 001 (COOL Chips, 2014)

Functional test generation guided by steady-state probabilities of abstract design. - Jian Wang; Huawei Li 001; Tao Lv 001; Tiancheng Wang; Xiaowei Li 001 (DATE, 2014)

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. - Yinhe Han 001; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2014)

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs. - Jun Zhou 022; Huawei Li 001; Yuntan Fang; Tiancheng Wang; Yuanqing Cheng; Xiaowei Li 001 (ISVLSI, 2014)

A novel abstraction-guided simulation approach using posterior probabilities for verification. - Jian Wang; Huawei Li 001; Xiaowei Li 001 (VLSI-DAT, 2014)

Reinventing Memory System Design for Many-Accelerator Architecture. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001 (J. Comput. Sci. Technol., 2014)

Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach. - Shuangde Fang; Zidong Du; Yuntan Fang; Yuanjie Huang; Yang Chen; Lieven Eeckhout; Olivier Temam; Huawei Li 001; Yunji Chen; Chengyong Wu (ACM Trans. Archit. Code Optim., 2014)

Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications. - Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Test-Quality Optimization for Variable $n$ -Detections of Transition Faults. - Dawen Xu 002; Huawei Li 001; Amirali Ghofrani; Kwang-Ting Cheng; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing. - Songwei Pei; Ye Geng; Huawei Li 001; Jun Liu; Song Jin (ASP-DAC, 2015)

A Lightweight Timing Channel Protection for Shared Memory Controllers. - Guopei Liu; Ying Wang 001; Sen Li; Huawei Li 001; Xiaowei Li 001 (ATS, 2015)

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs. - Jun Zhou 022; Huawei Li 001; Tiancheng Wang; Sen Li; Ying Wang 001; Xiaowei Li 001 (ATS, 2015)

TURO: A lightweight turn-guided routing scheme for 3D NoCs. - Jun Zhou 022; Huawei Li 001; Tiancheng Wang; Ying Wang 001; Xiaowei Li 001 (COOL Chips, 2015)

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2015)

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. - Ying Wang 001; Yinhe Han 001; Cheng Wang; Huawei Li 001; Xiaowei Li 001 (DAC, 2015)

Retraining-based timing error mitigation for hardware neural networks. - Jiachao Deng; Yuntan Fang; Zidong Du; Ying Wang 001; Huawei Li 001; Olivier Temam; Paolo Ienne; David Novo; Xiaowei Li 001; Yunji Chen; Chengyong Wu (DATE, 2015)

Temperature-aware software-based self-testing for delay faults. - Ying Zhang 040; Zebo Peng; Jianhui Jiang; Huawei Li 001; Masahiro Fujita (DATE, 2015)

A case of precision-tunable STT-RAM memory design for approximate neural network. - Ying Wang 001; Lili Song; Yinhe Han 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (ISCAS, 2015)

A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans. - Yun Cheng; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ISVLSI, 2015)

On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island. - Song Jin; Songwei Pei; Yinhe Han 001; Huawei Li 001 (VLSI-DAT, 2015)

An on-chip frequency programmable test clock generation and application method for small delay defect detection. - Songwei Pei; Huawei Li 001; Song Jin; Jun Liu; Xiaowei Li 001 (Integr., 2015)

Economizing TSV Resources in 3-D Network-on-Chip Design. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Binzhang Fu; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Data Remapping for Static NUCA in Degradable Chip Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools. - Yingxin Qiu; Huawei Li 001; Tiancheng Wang; Bo Liu 018; Yingke Gao; Xiaowei Li 001 (ATS, 2016)

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. - Ying Wang 001; Yinhe Han 001; Jun Zhou 022; Huawei Li 001; Xiaowei Li 001 (DAC, 2016)

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. - Ying Wang 001; Jie Xu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2016)

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2016)

PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping. - Faqiang Sun; Huawei Li 001; Yinhe Han 001; Guihai Yan; Jun Ma (IGSC, 2016)

An ultra-low overhead LUT-based PUF for FPGA. - Jiadong Wang; Aijiao Cui; Mengyang Li; Gang Qu 001; Huawei Li 001 (AsianHOST, 2016)

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2016)

A new countermeasure against scan-based side-channel attacks. - Yanhui Luo; Aijiao Cui; Gang Qu 001; Huawei Li 001 (ISCAS, 2016)

An accurate algorithm for computing mutation coverage in model checking. - Huina Chao; Huawei Li 001; Tiancheng Wang; Xiaowei Li 001; Bo Liu 018 (ITC, 2016)

Path constraint solving based test generation for observability-enhanced branch coverage. - Yanhong Zhou; Huawei Li 001; Tiancheng Wang; Bo Liu 018; Yingke Gao; Xiaowei Li 001 (VTS, 2016)

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs. - Jun Zhou 022; Huawei Li 001; Tiancheng Wang; Xiaowei Li 001 (Integr., 2016)

CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition. - Guihai Yan; Faqiang Sun; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Computers, 2016)

Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. - Jian Wang; Huawei Li 001; Tao Lv 001; Tiancheng Wang; Xiaowei Li 001; Sandip Kundu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. - Yanhong Zhou; Tiancheng Wang; Huawei Li 001; Tao Lv 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands. - Song Jin; Songwei Pei; Yinhe Han 001; Huawei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2016)

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Lei Zhang 008; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory. - Yibin Tang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2017)

On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios. - Huina Chao; Huawei Li 001; Xiaoyu Song; Tiancheng Wang; Xiaowei Li 001 (ATS, 2017)

A New Active IC Metering Technique Based on Locking Scan Cells. - Aijiao Cui; Xuesen Qian; Gang Qu 001; Huawei Li 001 (ATS, 2017)

Test and Reliability of Emerging Non-volatile Memories. - Said Hamdioui; Peyman Pouyan; Huawei Li 001; Ying Wang 001; Arijit Raychowdhury; Insik Yoon (ATS, 2017)

How to Secure Scan Design Against Scan-Based Side-Channel Attacks? - Wei Zhou; Aijiao Cui; Huawei Li 001; Gang Qu 001 (ATS, 2017)

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems. - Dawen Xu 002; Yi Liao; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (Conf. Computing Frontiers, 2017)

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2017)

Software-based online self-testing of network-on-chip using bounded model checking. - Ying Zhang 040; Krishnendu Chakrabarty; Huawei Li 001; Jianhui Jiang (ITC, 2017)

Flip-flop clustering based trace signal selection for post-silicon debug. - Yun Cheng; Huawei Li 001; Ying Wang 001; Yingke Gao; Bo Liu 018; Xiaowei Li 001 (VTS, 2017)

Innovative practices session 10C formal verification practices in industry. - Huawei Li 001; Xiaowei Li 001 (VTS, 2017)

Why current secure scan designs fail and how to fix them? - Aijiao Cui; Yanhui Luo; Huawei Li 001; Gang Qu 001 (Integr., 2017)

Retention-Aware DRAM Assembly and Repair for Future FGR Memories. - Ying Wang 001; Yinhe Han 001; Cheng Wang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. - Lili Song; Ying Wang 001; Yinhe Han 001; Huawei Li 001; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips. - Ying Wang 001; Jiachao Deng; Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Bias PUF based Secure Scan Chain Design. - Wenjie Li 004; Jing Ye 001; Xiaowei Li 001; Huawei Li 001; Yu Hu 001 (AsianHOST, 2018)

A low-overhead PUF based on parallel scan design. - Wenxuan Wang; Aijiao Cui; Gang Qu 001; Huawei Li 001 (ASP-DAC, 2018)

XORiM: A case of in-memory bit-comparator implementation and its performance implications. - Kaiwei Zou; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2018)

A New Scheme to Extract PUF Information by Scan Chain. - Aijiao Cui; Wei Zhou; Gang Qu 001; Huawei Li 001 (ATS, 2018)

Hardware Trojan Detection Based on Signal Correlation. - Wei Zhao; Haihua Shen; Huawei Li 001; Xiaowei Li 001 (ATS, 2018)

A retrospective evaluation of energy-efficient object detection solutions on embedded devices. - Ying Wang 001; Zhenyu Quan; Jiajun Li; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2018)

FCN-engine: accelerating deconvolutional layers in classic CNN processors. - Dawen Xu 002; Kaijie Tu; Ying Wang 001; Cheng Liu 008; Bingsheng He; Huawei Li 001 (ICCAD, 2018)

Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors. - Ying Wang 001; Wen Li; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2018)

Small Trojan Testing Using Bounded Model Checking. - Ying Zhang 040; Lu Yu; Huawei Li 001; Jianhui Jiang (ITC-Asia, 2018)

Lightweight Timing Channel Protection for Shared DRAM Controller. - Ying Wang 001; Wen Li; Huawei Li 001; Xiaowei Li 001 (ITC, 2018)

Innovative practices on challenges, opportunities, and solutions to hardware security. - Sohrab Aftabjahani; Jason Oberg; Michael Chen; Huawei Li 001 (VTS, 2018)

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. - Jing Ye 001; Qingli Guo; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2018)

CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency. - Faqiang Sun; Guihai Yan; Xin He; Huawei Li 001; Yinhe Han 001 (J. Comput. Sci. Technol., 2018)

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. - Yun Cheng; Huawei Li 001; Ying Wang 001; Haihua Shen; Bo Liu 018; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. - Ying Wang 001; Huawei Li 001; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. - Haihua Shen; Huazhe Tan; Huawei Li 001; Feng Zhang 014; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Resilient Neural Network Training for Accelerators with Computing Errors. - Dawen Xu 002; KouZi Xing; Cheng Liu 008; Ying Wang 001; Yulin Dai; Long Cheng 003; Huawei Li 001; Lei Zhang 008 (ASAP, 2019)

P3M: a PIM-based neural network model protection scheme for deep learning accelerator. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2019)

Exploring emerging CNFET for efficient last level cache design. - Dawen Xu 002; Li Li; Ying Wang 001; Cheng Liu 008; Huawei Li 001 (ASP-DAC, 2019)

GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network. - Renjie Lu; Haihua Shen; Yu Su; Huawei Li 001; Xiaowei Li 001 (ATS, 2019)

A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs. - Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (DAC, 2019)

Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Cong Shi 003; Xiaowei Li 001 (DAC, 2019)

Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. - Kaiwei Zou; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2019)

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. - Shengwen Liang; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (FPL, 2019)

An Agile Precision-Tunable CNN Accelerator based on ReRAM. - Yintao He; Ying Wang 001; Yongchen Wang; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2019)

RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCD, 2019)

Fuzzy Association Rule Mining Algorithm Based on Load Classifier. - Jing Chen; Hui Zheng 001; Peng Li 011; Zhenjiang Zhang; Huawei Li 001; Wei Liu 106 (ICDS, 2019)

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. - Kuozhong Zhang; Junying Huang; Jing Ye 001; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li 001; Xiaowei Li 001; Zhimin Zhang 004 (IOLTS, 2019)

Instruction Vulnerability Test and Code Optimization Against DVFS Attack. - Junying Huang; Jing Ye 001; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li 001; Xiaowei Li 001; Zhimin Zhang 004 (ITC-Asia, 2019)

Squeezing the Last MHz for CNN Acceleration on FPGAs. - Li Li; Dawen Xu 002; Kouzi Xing; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2019)

Implementation of Parametric Hardware Trojan in FPGA. - Yipei Yang; Jing Ye 001; Xiaowei Li 001; Yinhe Han 001; Huawei Li 001; Yu Hu 001 (ITC-Asia, 2019)

China Test Conference (CTC) - Extending the Global Test Forum to China. - Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (ITC, 2019)

A Memristor-based Scan Hold Flip-Flop. - Aijiao Cui; Zhenxing Chang; Ziming Wang; Gang Qu 001; Huawei Li 001 (NVMSA, 2019)

Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval. - Shengwen Liang; Ying Wang 001; Youyou Lu; Zhe Yang 012; Huawei Li 001; Xiaowei Li 001 (USENIX ATC, 2019)

A Secure and Low-overhead Active IC Metering Scheme. - Aijiao Cui; Yan Yang; Gang Qu 001; Huawei Li 001 (VTS, 2019)

Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2019)

Scan Chain Based Attacks and Countermeasures: A Survey. - Xiaowei Li 001; Wenjie Li 004; Jing Ye 001; Huawei Li 001; Yu Hu 001 (IEEE Access, 2019)

HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection. - Renjie Lu; Haihua Shen; Feng Zhang 014; Huawei Li 001; Wei Zhao; Xiaowei Li 001 (CoRR, 2019)

MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems. - Yibin Tang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ACM J. Emerg. Technol. Comput. Syst., 2019)

A QoS-QoR Aware CNN Accelerator Design Approach. - Ying Wang 001; Huawei Li 001; Long Cheng 003; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. - Yun Cheng; Huawei Li 001; Ying Wang 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. - Dawen Xu 002; Ziyang Zhu; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Lei Zhang 008; Kwang-Ting Cheng (ASAP, 2020)

Survey: Hardware Trojan Detection for Netlist. - Yipei Yang; Jing Ye 001; Yuan Cao 003; Jiliang Zhang 002; Xiaowei Li 001; Huawei Li 001; Yu Hu 001 (ATS, 2020)

Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. - Yixuan Zhao; Zhiteng Chao; Jing Ye 001; Wen Wang 007; Yuan Cao 003; Shuai Chen; Xiaowei Li 001; Huawei Li 001 (ATS, 2020)

Towards State-Aware Computation in ReRAM Neural Networks. - Yintao He; Ying Wang 001; Xiandong Zhao; Huawei Li 001; Xiaowei Li 001 (DAC, 2020)

An Efficient Deep Learning Accelerator for Compressed Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Yinhe Han 001; Xiaowei Li 001 (DAC, 2020)

CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. - Dawen Xu 002; Kexin Chu; Cheng Liu 008; Ying Wang 001; Lei Zhang 008; Huawei Li 001 (DATE, 2020)

HIT: A Hidden Instruction Trojan Model for Processors. - Jiaqi Zhang; Ying Zhang 040; Huawei Li 001; Jianhui Jiang (DATE, 2020)

Multi-task Scheduling for PIM-based Heterogeneous Computing System. - Dawen Xu 002; Cheng Chu; Cheng Liu 008; Ying Wang 001; Xianzhong Zhou; Lei Zhang 008; Huaguo Liang; Huawei Li 001 (ACM Great Lakes Symposium on VLSI, 2020)

Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. - Qingli Guo; Jing Ye 001; Jiliang Zhang 002; Yu Hu 001; Xiaowei Li 001; Huawei Li 001 (ACM Great Lakes Symposium on VLSI, 2020)

DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. - Shengwen Liang; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2020)

A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. - Ying Wang 001; Mengdi Wang; Bing Li 017; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2020)

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. - Rajendra Bishnoi; Lizhou Wu; Moritz Fieback; Christopher Münch; Sarath Mohanachandran Nair; Mehdi Baradaran Tahoori; Ying Wang 001; Huawei Li 001; Said Hamdioui (VTS, 2020)

Sequence Triggered Hardware Trojan in Neural Network Accelerator. - Zizhen Liu; Jing Ye 001; Xing Hu 001; Huawei Li 001; Xiaowei Li 001; Yu Hu 001 (VTS, 2020)

A New Secure Scan Design with PUF-based Key for Authentication. - Qidong Wang; Aijiao Cui; Gang Qu 001; Huawei Li 001 (VTS, 2020)

MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection. - Qingli Guo; Jing Ye 001; Yu Hu 001; Guohe Zhang; Xiaowei Li 001; Huawei Li 001 (IEEE Access, 2020)

Evaluating and Constraining Hardware Assertions with Absent Scenarios. - Huina Chao; Huawei Li 001; Xiaoyu Song; Tiancheng Wang; Xiaowei Li 001 (J. Comput. Sci. Technol., 2020)

A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash. - Aijiao Cui; Mengyang Li; Gang Qu 001; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

GPGPU-Based ATPG System: Myth or Reality? - Liyang Lai; Kun-Han Tsai; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Architecting Effectual Computation for Machine Learning Accelerators. - Hang Lu; Mingzhe Zhang; Yinhe Han 001; Qi Wang 025; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors. - Ying Zhang 040; Krishnendu Chakrabarty; Zebo Peng; Ahmed Rezine; Huawei Li 001; Petru Eles; Jianhui Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

SeGa: A Trojan Detection Method Combined With Gate Semantics. - Yunying Ye; Shan Li; Haihua Shen; Huawei Li 001; Xiaowei Li 001 (ATS, 2021)

GCiM: A Near-Data Processing Accelerator for Graph Construction. - Lei He 016; Cheng Liu 008; Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. - Yintao He; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

Scalable Parallel Static Learning. - Xiaoze Lin; Liyang Lai; Huawei Li 001 (ITC-Asia, 2021)

GLIST: Towards In-Storage Graph Learning. - Cangyuan Li; Ying Wang 001; Cheng Liu 008; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (USENIX ATC, 2021)

Special Session - Test for AI Chips: from DFT to On-line Testing. - Huawei Li 001; Xiaowei Li 001; Yu Huang 005; Ying Wang 001; Gary Guo (VTS, 2021)

Editorial for the special issue on reliability and power efficiency for HPC. - Jifeng He 001; Chenggang Wu 002; Huawei Li 001; Yang Guo 003; Tao Li 022 (CCF Trans. High Perform. Comput., 2021)

To cloud or not to cloud: an on-line scheduler for dynamic privacy-protection of deep learning workload on edge devices. - Yibin Tang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CCF Trans. High Perform. Comput., 2021)

Energy-Efficient Accelerator Design for Deformable Convolution Networks. - Dawen Xu 002; Cheng Chu; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (CoRR, 2021)

Taming Process Variations in CNFET for Efficient Last Level Cache Design. - Dawen Xu 002; Zhuangyu Feng; Cheng Liu 008; Li Li; Ying Wang 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (CoRR, 2021)

Efficient Secure Aggregation Based on SHPRG For Federated Learning. - Zizhen Liu; Si Chen; Jing Ye 001; Junfeng Fan; Huawei Li 001; Xiaowei Li 001 (CoRR, 2021)

Preface. - Huawei Li 001 (J. Comput. Sci. Technol., 2021)

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. - Shengwen Liang; Ying Wang 001; Cheng Liu 008; Lei He 016; Huawei Li 001; Dawen Xu 002; Xiaowei Li 001 (IEEE Trans. Computers, 2021)

An Edge 3D CNN Accelerator for Low-Power Activity Recognition. - Ying Wang 001; Yongchen Wang; Cong Shi 003; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. - Dawen Xu 002; Meng He 012; Cheng Liu 008; Ying Wang 001; Long Cheng 003; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. - Dawen Xu 002; Ziyang Zhu; Cheng Liu 008; Ying Wang 001; Shuang Zhao; Lei Zhang 008; Huaguo Liang; Huawei Li 001; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. - Jianan Mu; Yixuan Zhao; Zongyue Wang; Jing Ye 001; Junfeng Fan; Shuai Chen; Huawei Li 001; Xiaowei Li 001; Yuan Cao 003 (ASP-DAC, 2022)

A Hardware Trojan Trigger Localization Method in RTL based on Control Flow Features. - Hao Huang; Haihua Shen; Shan Li; Huawei Li 001 (ATS, 2022)

InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs. - Yintao He; Songyun Qu; Ying Wang 001; Bing Li 017; Huawei Li 001; Xiaowei Li 001 (DAC, 2022)

VStore: in-storage graph based vector search accelerator. - Shengwen Liang; Ying Wang 001; Ziming Yuan; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2022)

NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. - Fuping Li; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DATE, 2022)

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. - Fuping Li; Ying Wang 001; Yuanqing Cheng; Yujie Wang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2022)

Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. - Lei Dai; Ying Wang 001; Cheng Liu 008; Fuping Li; Huawei Li 001; Xiaowei Li 001 (ICCD, 2022)

Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. - Yixiao Chen; Jinfeng Song; Shuai Chen; Yuan Cao 003; Jing Ye 001; Huawei Li 001; Xiaowei Li 001; Xin Lou; Enyi Yao (ISOCC, 2022)

SASH: Efficient secure aggregation based on SHPRG for federated learning. - Zizhen Liu; Si Chen; Jing Ye 001; Junfeng Fan; Huawei Li 001; Xiaowei Li 001 (UAI, 2022)

Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective. - Cheng Liu 008; Zhen Gao 005; Siting Liu 001; Xuefei Ning; Huawei Li 001; Xiaowei Li 001 (VTS, 2022)

Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval. - Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CCF Trans. High Perform. Comput., 2022)

Fault-Tolerant Deep Learning: A Hierarchical Perspective. - Cheng Liu 008; Zhen Gao 005; Siting Liu 001; Xuefei Ning; Huawei Li 001; Xiaowei Li 001 (CoRR, 2022)

CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures. - Kaiwei Zou; Ying Wang 001; Long Cheng 003; Songyun Qu; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Computers, 2022)

Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing. - Yintao He; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning. - Cheng Liu 008; Cheng Chu; Dawen Xu 002; Ying Wang 001; Qianlong Wang; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Fast Precision Tuning Solution for Always-On DNN Accelerators. - Ying Wang 001; Yintao He; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding. - Aijiao Cui; Zhen Weng; Hui Zhang; Gang Qu 001; Huawei Li 001 (IEEE Trans. Emerg. Top. Comput., 2022)

Taming Process Variations in CNFET for Efficient Last-Level Cache Design. - Dawen Xu 002; Zhuangyu Feng; Cheng Liu 008; Li Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature. - Ying Zhang 040; Yi Ding; Zebo Peng; Huawei Li 001; Masahiro Fujita; Jianhui Jiang (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT. - Zhiteng Chao; Senlin Wang; Pengyu Tian; Shuwen Yuan; Huawei Li 001; Jing Ye 001; Xiaowei Li 001 (ATS, 2023)

Intelligent Automatic Test Pattern Generation for Digital Circuits Based on Reinforcement Learning. - Wenxing Li; Hongqin Lyu; Shengwen Liang; Tiancheng Wang; Pengyu Tian; Huawei Li 001 (ATS, 2023)

Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors. - Wen Li; Ying Wang 001; Kaiwei Zou; Huawei Li 001; Xiaowei Li 001 (ATS, 2023)

Message from the Chairs. - Huawei Li 001; Jing Ye 001; Wei Hu 008; Jiliang Zhang 002 (ATS, 2023)

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design. - Jianan Mu; Huajie Tan; Shuai Chen; Min Cai; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ATS, 2023)

A Template Attack on Reduction Without Reference Device on Kyber. - Yipei Yang; Junying Huang; Zongyue Wang; Jing Ye 001; Zihao Sun; Junfeng Fan; Shuai Chen; Huawei Li 001; Xiaowei Li 001; Yuan Cao 003 (ATS, 2023)

APPEND: Rethinking ASIP Synthesis in the Era of AI. - Cangyuan Li; Ying Wang 001; Huawei Li 001; Yinhe Han 001 (DAC, 2023)

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. - Jianan Mu; Huajie Tan; Jiawen Wu; Haotian Lu 002; Chip-Hong Chang; Shuai Chen; Shengwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2023)

Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. - Jiaxi Zhang 001; Shenggen Zheng; Liwei Ni; Huawei Li 001; Guojie Luo (DATE, 2023)

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. - Chaofang Ma; Jianan Mu; Jing Ye 001; Shuai Chen; Yuan Cao 003; Huawei Li 001; Xiaowei Li 001 (ETS, 2023)

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. - Erjing Luo; Haitong Huang; Cheng Liu 008; Guoyu Li; Bing Yang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2023)

Fast Exact NPN Classification with Influence-Aided Canonical Form. - Yonghe Zhang; Liwei Ni; Jiaxi Zhang 001; Guojie Luo; Huawei Li 001; Shenggen Zheng (ICCAD, 2023)

PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. - Yibo Du; Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (ICCD, 2023)

Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. - Liwei Ni; Zonglin Yang; Jiaxi Zhang 001; Junfeng Liu; Huawei Li 001; Biwei Xie; Xinquan Li (ICCD, 2023)

Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators. - Kaiwei Zou; Songyun Qu; Wen Li; Ying Wang 001; Huawei Li 001; Yongpan Liu (ICPADS, 2023)

BGNN-HT: Bidirectional Graph Neural Network for Hardware Trojan Cells Detection at Gate Level. - Peiheng Zhan; Haihua Shen; Shan Li; Huawei Li 001 (ISCAS, 2023)

Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers. - Xinghua Xue; Cheng Liu 008; Haitong Huang; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

ChipGPT: How far are we from natural language hardware design. - Kaiyan Chang; Ying Wang 001; Haimeng Ren; Mengdi Wang; Shengwen Liang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing. - Haitong Huang; Cheng Liu 008; Xinghua Xue; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library. - Xingquan Li; Simin Tao; Zengrong Huang; Shijian Chen; Zhisheng Zeng; Liwei Ni; Zhipeng Huang 009; Chunan Zhuang; Hongxi Wu; Weiguo Li; Xueyan Zhao; He Liu; et al. (CoRR, 2023)

Cross-Layer Optimization for Fault-Tolerant Deep Learning. - Qing Zhang; Cheng Liu 008; Bo Liu 018; Haitong Huang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA. - Liwei Ni; Zonglin Yang; Jiaxi Zhang 001; Changhong Feng; Jianhua Liu; Guojie Luo; Huawei Li 001; Biwei Xie; Xingquan Li (CoRR, 2023)

Chosen ciphertext correlation power analysis on Kyber. - Yipei Yang; Zongyue Wang; Jing Ye 001; Junfeng Fan; Shuai Chen; Huawei Li 001; Xiaowei Li 001; Yuan Cao 003 (Integr., 2023)

DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning. - Zizhen Liu; Si Chen; Jing Ye 001; Junfeng Fan; Huawei Li 001; Xiaowei Li 001 (J. Supercomput., 2023)

On-Line Fault Protection for ReRAM-Based Neural Networks. - Wen Li; Ying Wang 001; Cheng Liu 008; Yintao He; Lian Liu; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Computers, 2023)

Preface. - Weikang Qian; Ke Chen; Wei-Qiang Liu; Huawei Li 001 (J. Comput. Sci. Technol., 2023)

Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip. - Ying Zhang 040; Pengfei Ji; Pan-Wei Zhu; Zebo Peng; Huawei Li 001; Jian-Hui Jiang (J. Comput. Sci. Technol., 2023)

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. - Jianan Mu; Yi Ren; Wen Wang 007; Yizhong Hu; Shuai Chen; Chip-Hong Chang; Junfeng Fan; Jing Ye 001; Yuan Cao 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. - Cheng Chu; Cheng Liu 008; Dawen Xu 002; Ying Wang 001; Tao Luo 014; Huawei Li 001; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

Statistical Modeling of Soft Error Influence on Neural Networks. - Haitong Huang; Xinghua Xue; Cheng Liu 008; Ying Wang 001; Tao Luo 014; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. - Xinghua Xue; Cheng Liu 008; Bo Liu 018; Haitong Huang; Ying Wang 001; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Soft Error Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. - Zhiteng Chao; Xindi Zhang; Junying Huang; Jing Ye 001; Shaowei Cai 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction. - Lei Dai; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

iEDA: An Open-source infrastructure of EDA. - Xingquan Li; Zengrong Huang; Simin Tao; Zhipeng Huang 009; Chunan Zhuang; Hao Wang; Yifan Li; Yihang Qiu; Guojie Luo; Huawei Li 001; Haihua Shen; Mingyu Chen 001; et al. (ASPDAC, 2024)

Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. - Fuping Li; Ying Wang 001; Yujie Wang; Mengdi Wang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction. - Jiaping Tang; Zizhen Liu; Jianan Mu; Feng Gu; Mingjun Wang; Wenxing Li; Jing Ye 001; Xiaowei Li 001; Huawei Li 001 (ATS, 2024)

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. - Kaiyan Chang; Kun Wang 055; Nan Yang; Ying Wang 001; Dantong Jin; Wenlong Zhu; Zhirong Chen; Cangyuan Li; Hao Yan; Yunhao Zhou; Zhuoliang Zhao; Yuan Cheng; et al. (DAC, 2024)

Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. - Yibo Du; Ying Wang 001; Bing Li 017; Fuping Li; Shengwen Liang; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DAC, 2024)

SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning. - Wenxing Li; Hongqin Lyu; Shengwen Liang; Tiancheng Wang; Huawei Li 001 (DAC, 2024)

Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. - Lian Liu; Zhaohui Xu; Yintao He; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DAC, 2024)

Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. - Jianan Mu; Husheng Han; Shangyi Shi; Jing Ye 001; Zizhen Liu; Shengwen Liang; Meng Li 004; Mingzhe Zhang; Song Bian 001; Xing Hu 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2024)

GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. - Yibo Du; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DATE, 2024)

Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture. - Yintao He; Shixin Zhao; Songyun Qu; Huawei Li 001; Xiaowei Li 001; Ying Wang 001 (DATE, 2024)

HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System. - Shengwen Liang; Ziming Yuan; Ying Wang 001; Dawen Xu 002; Huawei Li 001; Xiaowei Li 001 (DATE, 2024)

A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. - Han Yan; Shuai Chen; Junying Huang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ETS, 2024)

Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization. - Yunkun Liao; Hanyue Lin; Jingya Wu; Wenyan Lu; Huawei Li 001; Xiaowei Li 001; Guihai Yan (Euro-Par (2), 2024)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. - Kaiyan Chang; Zhirong Chen; Yunhao Zhou; Wenlong Zhu; Kun Wang 055; Haobo Xu; Cangyuan Li; Mengdi Wang; Shengwen Liang; Huawei Li 001; Yinhe Han 001; Ying Wang 001 (ICCAD, 2024)

AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search. - Lei Dai; Ziming Yuan; Wen Li; Shengwen Liang; Kaiwei Zou; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. - Feng Gu; Mingjun Wang; Jianan Mu; Zizhen Liu; Jiaping Tang; Hui Wang 152; Yonghao Wang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

HLSPilot: LLM-based High-Level Synthesis. - Chenwei Xiong; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification. - Zhiteng Chao; Qinluan Dai; Jiale Li; Zizhen Liu; Wenxing Li; Hongqin Lyu; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2024)

Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262. - Mingjun Wang; Hui Wang 152; Jianan Mu; Zizhen Liu; Jun Gao; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2024)

ApproxPilot: A GNN-based Accelerator Approximation Framework. - Qing Zhang; Cheng Liu 008; Siting Liu 001; Yajuan Hui; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

SigDLA: A Deep Learning Accelerator Extension for Signal Processing. - Fangfa Fu; Wenyu Zhang; Zesong Jiang; Zhiyu Zhu; Guoyu Li; Bing Yang; Cheng Liu 008; Liyi Xiao; Jinxiang Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation. - Xinmiao Zhang 004; Zheng Feng; Shengwen Liang; Xinyu Chen 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA. - Zesong Jiang; Qing Zhang; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

MCU-MixQ: A HW/SW Co-optimized Mixed-precision Neural Network Design Framework for MCUs. - Junfeng Gong; Cheng Liu 008; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. - Mingkai Chen; Tianhua Han; Cheng Liu 008; Shengwen Liang; Kuai Yu; Lei Dai; Ziming Yuan; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis. - Liwei Ni; Rui Wang; Miao Liu; Xingyu Meng; Xiaoze Lin; Junfeng Liu; Guojie Luo; Zhufei Chu; Weikang Qian; Xiaoyan Yang; Biwei Xie; Xingquan Li; et al. (CoRR, 2024)

Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network. - Liwei Ni; Xinquan Li; Biwei Xie; Huawei Li 001 (CoRR, 2024)

SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. - Zizhen Liu; Weiyang He; Chip-Hong Chang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Inf. Forensics Secur., 2024)

Parallel Static Learning Toward Heterogeneous Computing Architectures. - Xiaoze Lin; Liyang Lai; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

PDG: A Prefetcher for Dynamic Graph Updating. - Xinmiao Zhang 004; Cheng Liu 008; Jiacheng Ni; Yuanqing Cheng; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference. - Lian Liu; Ying Wang 001; Xiandong Zhao; Weiwei Chen; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. - Mingkai Chen; Cheng Liu 008; Shengwen Liang; Lei He 016; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing. - Haitong Huang; Cheng Liu 008; Xinghua Xue; Bo Liu 018; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks. - Yintao He; Bing Li 017; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

On Modeling and Detecting Trojans in Instruction Sets. - Ying Zhang 040; Aodi He; Jiaying Li; Ahmed Rezine; Zebo Peng; Erik Larsson; Tao Yang; Jianhui Jiang; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. - Mingjun Wang; Hui Wang 152; Zizhen Liu; Feng Gu; Jianan Mu; Jiaping Tang; Jun Gao; Huawei Li 001; Jing Ye 001; Xiaowei Li 001 (ASP-DAC, 2025)

PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System. - Yintao He; Haiyu Mao; Christina Giannoula; Mohammad Sadrosadati; Juan Gómez-Luna; Huawei Li 001; Xiaowei Li 001; Ying Wang 001; Onur Mutlu (ASPLOS (2), 2025)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. - Jiaping Tang; Jianan Mu; Silin Liu; Zizhen Liu; Feng Gu; Xinyu Zhang; Leyan Wang; Shengwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2025)

NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search. - Ziming Yuan; Lei Dai; Wen Li; Jie Zhang 048; Shengwen Liang; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001; Jiafeng Guo; Peng Wang 037; Renhai Chen; et al. (HPCA, 2025)

FrontOrder: Frontier-Guided Graph Reordering. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Chenwei Xiong; Yu Zhang 027; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (ICDE, 2025)

Taijigraph: an Out-Of-Core Graph Processing System Enhanced with Computational Storage. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Hayden Kwok-Hay So; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IPDPS, 2025)

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs. - Peng Dang; Huawei Li 001; Wei Wang (ISCAS, 2025)

Frontier-guided Graph Reordering. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Chenwei Xiong; Yu Zhang 027; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (PPoPP, 2025)

HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. - Zhiteng Chao; Bin Sun; Hongqin Lyu; Ge Yu; Minjun Wang; Wenxing Li; Zizhen Liu; Jianan Mu; Shengwen Liang; Jing Ye 001; Xiaowei Li 001; Huawei Li 001 (VTS, 2025)

A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow. - Zhiteng Chao; Xindi Zhang; Junying Huang; Zizhen Liu; Yixuan Zhao; Jing Ye 001; Shaowei Cai 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2025)

APoX-M: Accelerate deep point cloud analysis via adaptive graph construction. - Lei Dai; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2025)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. - Jiaping Tang; Jianan Mu; Silin Liu; Zizhen Liu; Feng Gu; Xinyu Zhang; Leyan Wang; Shenwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2025)

Extend IVerilog to Support Batch RTL Fault Simulation. - Jiaping Tang; Jianan Mu; Zizhen Liu; Zhiteng Chao; Jing Ye 001; Huawei Li 001 (CoRR, 2025)

FUS: FPGA-based Universal Sketch with homogeneous and heterogeneous memory architectures. - Yunkun Liao; Jingya Wu; Wenyan Lu; Huawei Li 001; Xiaowei Li 001; Guihai Yan (CCF Trans. High Perform. Comput., 2025)

Large Processor Chip Model. - Kaiyan Chang; Mingzhi Chen; Yunji Chen; Zhirong Chen; Dongrui Fan; Junfeng Gong; Nan Guo; Yinhe Han 001; Qinfen Hao; Shuo Hou; Xuanjing Huang 001; Pengwei Jin; et al. (CoRR, 2025)

Functional Testing and Repair for ReRAM-Based Deep-Learning Accelerators. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Kaiwei Zou (IEEE Des. Test, 2025)

Oxpecker: Leaking Secrets via Fetch Target Queue. - Shan Li; Zheliang Xu; Haihua Shen; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)