A comparative study of the steady-state zones of German phones using centroids in the LPC parameter space. - Hubert Kaeslin (Speech Commun., 1986)

A systematic approach to the extraction of diphone elements from natural speech. - Hubert Kaeslin (IEEE Trans. Acoust. Speech Signal Process., 1986)

Application of Graph Theory to Topology Generation for Logic Gates. - Hubert Kaeslin (WG, 1988)

Behandlung der Umlaute bei der Verarbeitung deutscher Texte unter UNIX / How to Handle German Umlauts when Processing Documents under UNIX. - Hubert Kaeslin (it Inf. Technol., 1988)

Architectural design and realization of a single-chip Viterbi decoder. - Marc Biver; Hubert Kaeslin; Carlo Tommasini (Integr., 1989)

In-place updating of path metrics in Viterbi decoders. - Marc Biver; Hubert Kaeslin; Carlo Tommasini (IEEE J. Solid State Circuits, 1989)

VLSI Implementation of a New Block Cipher. - Heinz Bonnenberg; Andreas Curiger; Norbert Felber; Hubert Kaeslin; Xuejia Lai (ICCD, 1991)

Regular VLSI architectures for multiplication modulo (2n+1). - Andreas Curiger; Heinz Bonnenberg; Hubert Kaeslin (IEEE J. Solid State Circuits, 1991)

VINCI: Secure Test of a VLSI High-Speed Encryption System. - Heinz Bonnenberg; Andreas Curiger; Norbert Felber; Hubert Kaeslin; Reto Zimmermann; Wolfgang Fichtner (ITC, 1993)

A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm. - Reto Zimmermann; Andreas Curiger; Heinz Bonnenberg; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (IEEE J. Solid State Circuits, 1994)

Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits. - Robert Rogenmoser; Hubert Kaeslin; Tobias Blickle (PPSN, 1996)

The impact of transistor sizing on power efficiency in submicron CMOS circuits. - Robert Rogenmoser; Hubert Kaeslin (IEEE J. Solid State Circuits, 1997)

Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. - Manfred Stadler; Thomas Röwer; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner; Markus Thalmann (ITC, 1999)

A new paradigm for very flexible SONET/SDH IP-modules. - Thomas Roewer; Manfred Stadler; Markus Thalmann; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (CICC, 2000)

Design and Verification of a Stack Processor Virtual Component. - Manfred Stadler; Markus Thalmann; Thomas Röwer; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (IEEE Micro, 2001)

A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. - Thomas Villiger; Stephan Oetiker; Frank K. Gürkaynak; Norbert Felber; Hubert Kaeslin; Wolfgang Fichtner (ASYNC, 2002)

2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. - Adrian K. Lutz; Jürg Treichler; Frank K. Gürkaynak; Hubert Kaeslin; Gérard Basler; Antonia Erni; Stephan Reichmuth; Pieter Rommens; Stephan Oetiker; Wolfgang Fichtner (CHES, 2002)

Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. - Thomas Villiger; Hubert Kaeslin; Frank K. Gürkaynak; Stephan Oetiker; Wolfgang Fichtner (ASYNC, 2003)

Variable delay ripple carry adder with carry chain interrupt detection. - Andreas Burg 001; Frank K. Gürkaynak; Hubert Kaeslin; Wolfgang Fichtner (ISCAS (5), 2003)

Waveform coding for low-power digital filtering of speech data. - Jürgen Wassner; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (IEEE Trans. Signal Process., 2003)

Towards an AES crypto-chip resistant to differential power analysis. - Norbert Pramstaller; Frank K. Gürkaynak; Simon Haene; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (ESSCIRC, 2004)

A 2 Gb/s balanced AES crypto-chip implementation. - Frank K. Gürkaynak; Andreas Burg 001; Norbert Felber; Wolfgang Fichtner; D. Gasser; Franco Hug; Hubert Kaeslin (ACM Great Lakes Symposium on VLSI, 2004)

A 0.67-mm2 45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aids. - Flavio Carbognani; Felix Bürgin; Luca Henzen; Herbert Koch; Hovig Magdassian; Christoph Pedretti; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (ECCTD, 2005)

Improving DPA security by using globally-asynchronous locally-synchronous systems. - Frank K. Gürkaynak; Stephan Oetiker; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (ESSCIRC, 2005)

Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. - Flavio Carbognani; Felix Bürgin; Norbert Felber; Hubert Kaeslin; Wolfgang Fichtner (PATMOS, 2005)

Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. - Frank K. Gürkaynak; Stephan Oetiker; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (FMGALS@MEMOCODE, 2005)

GALS at ETH Zurich: Success or Failure. - Frank K. Gürkaynak; Stephan Oetiker; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (ASYNC, 2006)

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. - Felix Bürgin; Flavio Carbognani; Martin Hediger; Hektor Meier; Robert Meyer-Piening; Rafael Santschi; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (DAC, 2006)

Two-phase resonant clocking for ultra-low-power hearing aid applications. - Flavio Carbognani; Felix Bürgin; Norbert Felber; Hubert Kaeslin; Wolfgang Fichtner (DATE, 2006)

42% power savings through glitch-reducing clocking strategy in a hearing aid application. - Flavio Carbognani; Felix Bürgin; Norbert Felber; Hubert Kaeslin; Wolfgang Fichtner (ISCAS, 2006)

A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication. - Flavio Carbognani; Simon Haene; Manuel Arrigo; Claudio Pagnamenta; Felix Bürgin; Norbert Felber; Hubert Kaeslin; Wolfgang Fichtner (CICC, 2007)

A hardware architecture for surface splatting. - Tim Weyrich; Simon Heinzle; Timo Aila; Daniel Bernhard Fasnacht; Stephan Oetiker; Mario Botsch; Cyril Flaig; Simon Mall; Kaspar Rohrer; Norbert Felber; Hubert Kaeslin; Markus H. Gross (ACM Trans. Graph., 2007)

Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison. - Peter Luethi; Christoph Studer; Sebastian Duetsch; Eugen Zgraggen; Hubert Kaeslin; Norbert Felber; Wolfgang Fichtner (APCCAS, 2008)

Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. - Flavio Carbognani; Felix Bürgin; Norbert Felber; Hubert Kaeslin; Wolfgang Fichtner (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Sparsity-based real-time audio restoration. - Patrick Maechler; David E. Bellasi; Andreas Burg 001; Norbert Felber; Hubert Kaeslin; Christoph Studer (DASIP, 2012)

Compressive sensing for WiFi-based passive bistatic radar. - Patrick Maechler; Norbert Felber; Hubert Kaeslin (EUSIPCO, 2012)

High-speed compressed sensing reconstruction on FPGA using OMP and AMP. - Lin Bai 002; Patrick Maechler; Michael Muehlberghuber; Hubert Kaeslin (ICECS, 2012)

Hardware-efficient random sampling of fourier-sparse signals. - Patrick Maechler; Norbert Felber; Hubert Kaeslin; Andreas Burg 001 (ISCAS, 2012)

VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing. - Patrick Maechler; Christoph Studer; David E. Bellasi; Arian Maleki; Andreas Burg 001; Norbert Felber; Hubert Kaeslin; Richard G. Baraniuk (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications. - Pierre Greisen; Michael Schaffner; Simon Heinzle; Marian Runo; Aljoscha Smolic; Andreas Burg 001; Hubert Kaeslin; Markus H. Gross (IEEE Trans. Circuits Syst. Video Technol., 2012)

MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping. - Michael Schaffner; Pierre Greisen; Simon Heinzle; Frank K. Gürkaynak; Hubert Kaeslin; Aljoscha Smolic (ESSCIRC, 2013)

Live demonstration: Real-time audio restoration using sparse signal recovery. - David E. Bellasi; Patrick Maechler; Andreas Burg 001; Norbert Felber; Hubert Kaeslin; Christoph Studer (ISCAS, 2013)

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized. - Michael Schaffner; Pascal A. Hager; Lukas Cavigelli; Z. Fang; Pierre Greisen; Frank K. Gürkaynak; Aljoscha Smolic; Hubert Kaeslin; Luca Benini (VLSI-SoC (Selected Papers), 2013)

A real-time 720p feature extraction core based on Semantic Kernels Binarized. - Michael Schaffner; Pascal Hager; Lukas Cavigelli; Pierre Greisen; Frank K. Gürkaynak; Hubert Kaeslin (VLSI-SoC, 2013)

Evaluation and FPGA Implementation of Sparse Linear Solvers for Video Processing Applications. - Pierre Greisen; Marian Runo; Patrice Guillet; Simon Heinzle; Aljoscha Smolic; Hubert Kaeslin; Markus H. Gross (IEEE Trans. Circuits Syst. Video Technol., 2013)

SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC. - Michael Gautschi; Michael Muehlberghuber; Andreas Traber; Sven Stucki; Matthias Baer; Renzo Andri; Luca Benini; Beat Muheim; Hubert Kaeslin (ASAP, 2014)

An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. - Michael Schaffner; Frank K. Gürkaynak; Aljoscha Smolic; Hubert Kaeslin; Luca Benini (DAC, 2014)

Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. - Christoph Keller; Frank K. Gürkaynak; Hubert Kaeslin; Norbert Felber (ISCAS, 2014)

Automatic multiview synthesis - Towards a mobile system on a chip. - Michael Schaffner; Frank K. Gürkaynak; Hubert Kaeslin; Luca Benini; Aljosa Smolic (VCIP, 2015)

Automatic multiview synthesis - Prototype demo. - Michael Schaffner; Frank K. Gürkaynak; Hubert Kaeslin; Luca Benini; Aljosa Smolic (VCIP, 2015)

Semiconductor Technology and the Energy Efficiency of ICT. - Hubert Kaeslin (ICT Innovations for Sustainability, 2015)

Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW. - Michael Schaffner; Frank K. Gürkaynak; Pierre Greisen; Hubert Kaeslin; Luca Benini; Aljosa Smolic (IEEE Trans. Circuits Syst. Video Technol., 2016)

Towards Edge-Aware Spatio-Temporal Filtering in Real-Time. - Michael Schaffner; Florian Scheidegger; Lukas Cavigelli; Hubert Kaeslin; Luca Benini; Aljosa Smolic (IEEE Trans. Image Process., 2018)