Input don't care sequences in FSM networks. - Huey-Yih Wang; Robert K. Brayton (ICCAD, 1993)

HSIS: A BDD-Based Environment for Formal Verification. - Adnan Aziz; Felice Balarin; Szu-Tsung Cheng; Ramin Hojati; Timothy Kam; Sriram C. Krishnan; Rajeev K. Ranjan 001; Thomas R. Shiple; Vigyan Singhal; Serdar Tasiran; Huey-Yih Wang; Robert K. Brayton; et al. (DAC, 1994)

Permissible Observability Relations in FSM Networks. - Huey-Yih Wang; Robert K. Brayton (DAC, 1994)

Multi-level logic optimization of FSM networks. - Huey-Yih Wang; Robert K. Brayton (ICCAD, 1995)