An architecture of high-performance frequency and phase synthesis. - Hugh Mair; Liming Xiu (IEEE J. Solid State Circuits, 2000)

A design platform for 90-nm leakage reduction techniques. - Philippe Royannez; Hugh Mair; Franck Dahan; Mike Wagner; Mark Streeter; Laurent Bouetel; Joel Blasquez; H. Clasen; G. Semino; Julie Dong; D. Scott; B. Pitts; et al. (DAC, 2005)

Solutions for logic and processor core design at the 45nm technology node & and below. - Philippe Royannez; Hugh Mair; Michael Clinton; Uming Ko (ICECS, 2007)

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. - Gordon Gammie; Alice Wang; Minh Chau; Sumanth Gururajarao; Robert Pitts; Fabien Jumel; Stacey Engel; Philippe Royannez; Rolf Lagerquist; Hugh Mair; Jeff Vaccani; Greg Baldwin; et al. (ISSCC, 2008)

SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. - Gordon Gammie; Alice Wang; Hugh Mair; Rolf Lagerquist; Minh Chau; Philippe Royannez; Sumanth Gururajarao; Uming Ko (Proc. IEEE, 2010)

A 28nm 0.6V low-power DSP for mobile applications. - Gordon Gammie; Nathan Ickes; Mahmut E. Sinangil; Rahul Rithe; Jie Gu 007; Alice Wang; Hugh Mair; Satyendra Datla; Bing Rong; Sushma Honnavara Prasad; Lam Ho; Greg Baldwin; et al. (ISSCC, 2011)

Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver. - Andrew K. Joy; Hugh Mair; Hae-Chang Lee; Arnold Feldman; Clemenz L. Portmann; Neil Bulman; Eugenia Cordero Crespo; Peter Hearne; Patty Huang; Ben Kerr; Pulkit Khandelwal; Franz Kuhlmann; et al. (ISSCC, 2011)

A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V. - Mahmut E. Sinangil; Hugh Mair; Anantha P. Chandrakasan (ISSCC, 2011)

A 28 nm 0.6 V Low Power DSP for Mobile Applications. - Nathan Ickes; Gordon Gammie; Mahmut E. Sinangil; Rahul Rithe; Jie Gu 007; Alice Wang; Hugh Mair; Satyendra Datla; Bing Rong; Sushma Honnavara Prasad; Lam Ho; Greg Baldwin; et al. (IEEE J. Solid State Circuits, 2012)

23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques. - Hugh Mair; Gordon Gammie; Alice Wang; Sumanth Gururajarao; Ichiro Lin; HsinChen Chen; Wuan Kuo; Anand Rajagopalan; Wei-Zheng Ge; Rolf Lagerquist; Syed Rahman; C. J. Chung; et al. (ISSCC, 2015)

4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance. - Hugh Mair; Gordon Gammie; Alice Wang; Rolf Lagerquist; C. J. Chung; Sumanth Gururajarao; Ping Kao; Anand Rajagopalan; Anirban Saha; Amit Jain; Ericbill Wang; Shichin Ouyang; et al. (ISSCC, 2016)

Session 17 overview: SRAM. - Hugh Mair; Atsushi Kawasumi (ISSCC, 2016)

3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. - Hugh Mair; Ericbill Wang; Alice Wang; Ping Kao; Yuwen Tsai; Sumanth Gururajarao; Rolf Lagerquist; Jin Son; Gordon Gammie; Gordon Lin; Achuta Thippana; Kent Li; et al. (ISSCC, 2017)

2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC. - Hugh Mair; Ericbill Wang; Ashish Nayak; Rolf Lagerquist; Loda Chou; Gordon Gammie; HsinChen Chen; Lee-Kee Yong; Manzur Rahman; Jenny Wiedemeier; Ramu Madhavaram; Alex Chiou; et al. (ISSCC, 2020)

A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem. - HsinChen Chen; Rolf Lagerquist; Ashish Nayak; Hugh Mair; Gokulakrishnan Manoharan; Ericbill Wang; Gordon Gammie; Efron Ho; Anand Rajagopalan; Lee-Kee Yong; Ramu Madhavaram; Madhur Jagota; et al. (ISSCC, 2021)

SE1: What Technologies Will Shape the Future of Computing? - Hugh Mair; Shinichiro Shiratake; Eric Karl; Thomas Burd; Jonathan Chang; Debbie Marr; Samuel Naffziger; Henk Corporaal; Ken Takeuchi; Naresh R. Shanbhag (ISSCC, 2021)

Session 4 Overview: Processors Digital Architectures and Systems Subcommittee. - Sanu Mathew; Shidhartha Das; Hugh Mair (ISSCC, 2021)

A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. - Ashish Nayak; HsinChen Chen; Hugh Mair; Rolf Lagerquist; Tao Chen; Anand Rajagopalan; Gordon Gammie; Ramu Madhavaram; Madhur Jagota; C. J. Chung; Jenny Wiedemeier; Bala Meera; et al. (ISSCC, 2022)

A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET. - Bo-Jr Huang; Alfred Tsai; Lear Hsieh; Kathleen Chang; C.-J. Tsai; Jia-Ming Chen; Eric Jia-Wei Fang; Sung S.-Y. Hsueh; Jack Ciao; Barry Chen; Chuck Chang; Ping Kao; et al. (ISSCC, 2023)

14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU. - Chien-Yu Lu; Bo-Jr Huang; Min-Chieh Chen; Ollie Tsai; Alfred Tsai; Eric Jia-Wei Fang; Yuju Cho; Harry H. Chen; Ping Kao; Ericbill Wang; Hugh Mair; Shih-Arn Hwang (ISSCC, 2024)

2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC. - Anshul Varma; Sumanth Gururajarao; HsinChen Chen; Tao Chen; Gordon Gammie; Hugh Mair; Jen-Hang Yang; Hao-Hsiang Yu; Shun-Chieh Chang; Cheng-Hao Yang; Li-An Huang; Kumar Ramanathan; et al. (ISSCC, 2024)

8.2: Run-Time Power Management System by on-Die Power Sensor with Silicon Machine Learning-Based Calibration in a 3nm Octa-Core CPU. - Chien-Yu Lu; Bo-Jr Huang; Min-Chieh Chen; Alfred Tsai; Eric Jia-Wei Fang; Yuju Cho; Rex Che-Yuan Liu; Ericbill Wang; You-Ming Tsao; Hugh Mair; Shih-Arn Hwang (ISSCC, 2025)