23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface. - Young-Sub Yuk; Seungchul Jung; Hui-Dong Gwon; Sukhwan Choi; Si-Duk Sung; Tae-Hwang Kong; Sung-Wan Hong; Jun-Han Choi; Min-Yong Jeong; Jong-Pil Im; Seung-Tak Ryu; Gyu-Hyeong Cho (ISSCC, 2014)

PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator. - Young-sub Yuk; Seungchul Jung; Chul Kim; Hui-Dong Gwon; Sukhwan Choi; Gyu-Hyeong Cho (IEEE Trans. Very Large Scale Integr. Syst., 2014)

5.2 An 8Ω 10W 91%-power-efficiency 0.0023%-THD+N multi-level Class-D audio amplifier with folded PWM. - Ji-Hun Lee; Jun-Suk Bang; Kiduk Kim; Hui-Dong Gwon; Sang-Hui Park; Yeunhee Huh; Kye-Seok Yoon; Jong-Beom Baek; Yong-Min Ju; Gibbeum Lee; Homin Park; Hyeon-Min Bae; et al. (ISSCC, 2017)

Voltage-Boosted Current-Mode Wireless Power Receiver for Directly Charging a Low-Voltage Battery in Implantable Medical Systems. - Sang-Han Lee; Jun-Suk Bang; Kye-Seok Yoon; Hui-Dong Gwon; Sang-Won Kim 001; In-Kui Cho; Sung-Wan Hong; Gyu-Hyeong Cho (IEEE Trans. Ind. Electron., 2019)

A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS. - Jun-Hwan Jang; Hui-Dong Gwon; Tae-Hwang Kong; Jun-Hyeok Yang; Byong-Deok Choi (IEEE J. Solid State Circuits, 2022)

A 0.5-1-V Time-Voltage Hybrid Domain Dual- Loop Analog LDO With Wide-Bandwidth High PSR in 28 nm. - Jun-Hwan Jang; Hui-Dong Gwon; Sungmin Yoo; Jun-Hyeok Yang; Byong-Deok Choi (IEEE J. Solid State Circuits, 2025)