Hui Guo
Affiliations:- University of New South Wales, Sydney, NSW, Australia
According to our database1,
Hui Guo
authored at least 36 papers
between 1997 and 2021.
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Bibliography
2021
Microprocess. Microsystems, September, 2021
2019
DEFT: Dynamic Fault-Tolerant Elastic scheduling for tasks with uncertain runtime in cloud.
Inf. Sci., 2019
2018
SP-Partitioner: A novel partition method to handle intermediate data skew in spark streaming.
Future Gener. Comput. Syst., 2018
A Bandwidth-Aware Authentication Scheme for Packet-Integrity Attack Detection on Trojan Infected NoC.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
2017
iCETD: An improved tag generation design for memory data authentication in embedded processor systems.
Integr., 2017
Proceedings of the 2017 International Conference on Cryptography, Security and Privacy, 2017
2016
Fault-Tolerant Scheduling for Real-Time Scientific Workflows with Elastic Resource Provisioning in Virtualized Clouds.
IEEE Trans. Parallel Distributed Syst., 2016
EONS: Minimizing Energy Consumption for Executing Real-Time Workflows in Virtualized Cloud Data Centers.
Proceedings of the 45th International Conference on Parallel Processing Workshops, 2016
Data-Space Relocation to Improve Data Cache Performance for Embedded Multi-threaded Processor Systems.
Proceedings of the Fifth International Conference on Network, Communication and Computing, 2016
Improving tag generation for memory data authentication in embedded processor systems.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Towards energy-efficient scheduling for real-time tasks under uncertain cloud computing environment.
J. Syst. Softw., 2015
Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
2014
Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and Implementation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
Dynamic encryption key design and management for memory data encryption in embedded systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
2012
Rolling-horizon scheduling for energy constrained distributed real-time embedded systems.
J. Syst. Softw., 2012
Proceedings of the 15th International Conference on Compilers, 2012
2011
Microprocess. Microsystems, 2011
Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems.
Int. J. Handheld Comput. Res., 2011
2010
Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems.
J. Syst. Archit., 2010
Proceedings of the Ubiquitous Computing and Multimedia Applications, 2010
Proceedings of the Future Generation Information Technology, 2010
Enabling large decoded instruction loop caching for energy-aware embedded processors.
Proceedings of the 2010 International Conference on Compilers, 2010
2009
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors.
IET Comput. Digit. Tech., 2009
An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction.
EURASIP J. Embed. Syst., 2009
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009
A Segmental Bus-invert Coding Method for Instruction Memory Data Bus Power Efficiency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Proceedings of the Second International Conference on Future Generation Communication and Networking, 2008
2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Application specific forwarding network and instruction encoding for multi-pipe ASIPs.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
1998
Proceedings of the ASP-DAC '98, 1998
1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997