Power consumption in CMOS combinational logic blocks at high frequencies. - Sri Parameswaran; Hui Guo 001 (ASP-DAC, 1997)

Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. - Hui Guo 001; Sri Parameswaran (ASP-DAC, 1998)

Power Reduction in Pipelines. - Sri Parameswaran; Hui Guo 001 (ASP-DAC, 1998)

Dual-pipeline heterogeneous ASIP design. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran (CODES+ISSS, 2004)

Balancing System Level Pipelines with Stage Voltage Scaling. - Hui Guo 001; Sri Parameswaran (ISVLSI, 2005)

Application specific forwarding network and instruction encoding for multi-pipe ASIPs. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran; Aleksandar Ignjatovic (CODES+ISSS, 2006)

Customization of application specific heterogeneous multi-pipeline processors. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran (DATE, 2006)

Security Design for Multi-service Smart Card Systems. - Mei Hong; Hui Guo 001; Bin Luo 001 (FGCN (1), 2008)

A Segmental Bus-invert Coding Method for Instruction Memory Data Bus Power Efficiency. - Ji Gu; Hui Guo 001 (ISCAS, 2009)

ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems. - Ji Gu; Hui Guo 001; Patrick Li (RTCSA, 2009)

An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction. - Ji Gu; Hui Guo 001 (EURASIP J. Embed. Syst., 2009)

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. - Swarnalatha Radhakrishnan; Hui Guo 001; Sri Parameswaran; Aleksandar Ignjatovic (IET Comput. Digit. Tech., 2009)

Enabling large decoded instruction loop caching for energy-aware embedded processors. - Ji Gu; Hui Guo 001 (CASES, 2010)

FEDTIC: A Security Design for Embedded Systems with Insecure External Memory. - Mei Hong; Hui Guo 001 (FGIT, 2010)

An Energy Efficient Instruction Prefetching Scheme for Embedded Processors. - Ji Gu; Hui Guo 001 (UCMA, 2010)

Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems. - Hui Guo 001; Sri Parameswaran (J. Syst. Archit., 2010)

Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems. - Ji Gu; Hui Guo 001 (Int. J. Handheld Comput. Res., 2011)

An on-chip instruction cache design with one-bit tag for low-power embedded systems. - Ji Gu; Hui Guo 001; Patrick Li (Microprocess. Microsystems, 2011)

A cost-effective tag design for memory data authentication in embedded systems. - Mei Hong; Hui Guo 001; Xiaobo Sharon Hu (CASES, 2012)

Rolling-horizon scheduling for energy constrained distributed real-time embedded systems. - Chuan He; Xiaomin Zhu 001; Hui Guo 001; Dishan Qiu; Jianqing Jiang (J. Syst. Softw., 2012)

Dynamic encryption key design and management for memory data encryption in embedded systems. - Mei Hong; Hui Guo 001; Sri Parameswaran (ISVLSI, 2013)

DLIC: Decoded loop instructions caching for energy-aware embedded processors. - Ji Gu; Hui Guo 001; Tohru Ishihara (ACM Trans. Embed. Comput. Syst., 2013)

Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and Implementation. - Mahanama Wickramasinghe; Hui Guo 001 (ISVLSI, 2014)

Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors. - Mahanama Wickramasinghe; Hui Guo 001 (ICCD, 2015)

Towards energy-efficient scheduling for real-time tasks under uncertain cloud computing environment. - Huangke Chen; Xiaomin Zhu 001; Hui Guo 001; Jianghan Zhu; Xiao Qin 001; Jianhong Wu (J. Syst. Softw., 2015)

Improving tag generation for memory data authentication in embedded processor systems. - Tao Liu; Hui Guo 001; Sri Parameswaran; Xiaobo Sharon Hu (ASP-DAC, 2016)

Data-Space Relocation to Improve Data Cache Performance for Embedded Multi-threaded Processor Systems. - Mahanama Wickramasinghe; Hui Guo 001 (ICNCC, 2016)

EONS: Minimizing Energy Consumption for Executing Real-Time Workflows in Virtualized Cloud Data Centers. - Huangke Chen; Xiaomin Zhu 001; Dishan Qiu; Hui Guo 001; Laurence T. Yang; Peizhong Lu (ICPP Workshops, 2016)

Fault-Tolerant Scheduling for Real-Time Scientific Workflows with Elastic Resource Provisioning in Virtualized Clouds. - Xiaomin Zhu 001; Ji Wang 002; Hui Guo 001; Dakai Zhu 001; Laurence T. Yang; Ling Liu 001 (IEEE Trans. Parallel Distributed Syst., 2016)

Packet Leak Detection on Hardware-Trojan Infected NoCs for MPSoC Systems. - Mubashir Hussain; Hui Guo 001 (ICCSP, 2017)

iCETD: An improved tag generation design for memory data authentication in embedded processor systems. - Tao Liu; Hui Guo 001; Sri Parameswaran; Xiaobo Sharon Hu (Integr., 2017)

EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip. - Mubashir Hussain; Amin Malekpour; Hui Guo 001; Sri Parameswaran (ISVLSI, 2018)

A Bandwidth-Aware Authentication Scheme for Packet-Integrity Attack Detection on Trojan Infected NoC. - Mubashir Hussain; Hui Guo 001 (VLSI-SoC, 2018)

SP-Partitioner: A novel partition method to handle intermediate data skew in spark streaming. - Guipeng Liu; Xiaomin Zhu 001; Ji Wang 002; Deke Guo; Weidong Bao 001; Hui Guo 001 (Future Gener. Comput. Syst., 2018)

DEFT: Dynamic Fault-Tolerant Elastic scheduling for tasks with uncertain runtime in cloud. - Hui Yan; Xiaomin Zhu 001; Huangke Chen; Hui Guo 001; Wen Zhou; Weidong Bao 001 (Inf. Sci., 2019)

COPS: A complete oblivious processing system. - Sajid Hussain; Hui Guo 001; Tuo Li 001; Hassaan Saadat; Sri Parameswaran (Microprocess. Microsystems, 2021)

MP-ORAM: A Novel ORAM Design for Multicore Processor Systems. - Sajid Hussain; Hui Guo 001; Tuo Li 001; Sri Parameswaran (IEEE Trans. Dependable Secur. Comput., 2024)