A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)