A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement. - Jen-Huan Tsai; Sheng-An Ko; Hui-Huan Wang; Chia-Wei Wang; Hsin Chen; Po-Chiun Huang (A-SSCC, 2014)

A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry. - Jen-Huan Tsai; Hui-Huan Wang; Yen-Ju Chen; Yen-Hsin Wei; Yo-Hsien Kao; Yang-Chi Yen; Po-Chiun Huang; Meng-Hung Shen; Hsin Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics. - Jen-Huan Tsai; Sheng-An Ko; Chia-Wei Wang; Yang-Chi Yen; Hui-Huan Wang; Po-Chiun Huang; Po-Hsiang Lan; Meng-Hung Shen (IEEE J. Solid State Circuits, 2015)

A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching. - Jen-Huan Tsai; Hui-Huan Wang; Yang-Chi Yen; Chang-Ming Lai; Yen-Ju Chen; Po-Chiun Huang; Ping-Hsuan Hsieh; Hsin Chen; Chao-Cheng Lee (IEEE J. Solid State Circuits, 2015)