Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1992)

Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1994)

Complete Test Set for Multiple-Valued Logic Networks. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1994)

On Designing of 4-Valued Memory with Double-Gate TFT. - Chung-Len Lee; Horng Nan Chern; Min Shung Liao; Hui Min Wang (ISMVL, 1995)

Factorization of Multi-Valued Logic Functions. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1995)

A network representation method based on edge information extraction. - Wei Fan 001; Hui Min Wang; Yan Xing; Rui Huang 006; W. H. Ip; Kai-Leung Yung (Soft Comput., 2020)