An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits. - Huazhong Yang; Rong Luo; Hui Wang 004; Runsheng Liu (ASP-DAC, 1999)

Noise estimation for deep sub-micron integrated circuits. - Bin Chen; Huazhong Yang; Hui Wang 004 (Sci. China Ser. F Inf. Sci., 2001)

An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits. - Gang Huang; Huazhong Yang; Rong Luo; Hui Wang 004 (Sci. China Ser. F Inf. Sci., 2002)

A Hierarchical Approach for Incremental Floorplan Based on Genetic Algorithms. - Yongpan Liu; Huazhong Yang; Rong Luo; Hui Wang 004 (ICNC (3), 2005)

Improved Multiuser Detection for Fast FH/MFSK Systems. - Hui Zhang 013; Huazhong Yang; Shuzheng Xu; Hui Wang 004 (ICWN, 2005)

Application of DAPSK in HF communications. - Shuzheng Xu; Huazhong Yang; Hui Wang 004 (IEEE Commun. Lett., 2005)

A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices. - Saihua Lin; Rong Luo; Huazhong Yang; Hui Wang 004 (APCCAS, 2006)

A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection. - Yongpan Liu; Yu Wang 002; Feng Zhang 014; Rong Luo; Hui Wang 004 (APCCAS, 2006)

Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate. - Yu Wang 002; Hui Wang 004; Huazhong Yang (APCCAS, 2006)

Sigma-delta based clock recovery using on-chip PLL in FPGA. - Ning Ge 001; Yuyu Liu; Huazhong Yang; Hui Wang 004 (FPT, 2006)

Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits. - Yu Wang 002; Yongpan Liu; Rong Luo; Huazhong Yang; Hui Wang 004 (ISLPED, 2006)

Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization. - Yu Wang 002; Hai Lin; Huazhong Yang; Rong Luo; Hui Wang 004 (ISQED, 2006)

IR-drop Reduction Through Combinational Circuit Partitioning. - Hai Lin; Yu Wang 002; Rong Luo; Huazhong Yang; Hui Wang 004 (PATMOS, 2006)

Modeling the Impact of Process Variation on Critical Charge Distribution. - Qian Ding; Rong Luo; Hui Wang 004; Huazhong Yang; Yuan Xie 001 (SoCC, 2006)

A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator. - Jun Chen; Rong Luo; Huazhong Yang; Hui Wang 004 (VLSI Design, 2006)

Signal-Path-Level Dual-VT Assignment for Leakage Power Reduction. - Yu Wang 002; Huazhong Yang; Hui Wang 004 (J. Circuits Syst. Comput., 2006)

A Hybrid Genetic Algorithm with Critical Primary Inputs Sharing and Minor Primary Inputs Bits Climbing for Circuit Maximum Power Estimation. - Zhixin Tian; Yongpan Liu; Huazhong Yang; Hui Wang 004 (ICNC (4), 2007)

Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems. - Yongpan Liu; Huazhong Yang; Robert P. Dick; Hui Wang 004; Li Shang (ISQED, 2007)

Phase noise analysis of oscillators with Sylvester representation for periodic time-varying modulus matrix by regular perturbations. - JianXing Fan; Huazhong Yang; Hui Wang 004; Xiaolang Yan; Chaohuan Hou (Sci. China Ser. F Inf. Sci., 2007)

Modified Conditional-Precharge Sense-amplifier-Based Flip-Flop with Improved Speed. - Fei Qiao; Huazhong Yang; Dingli Wei; Hui Wang 004 (J. Circuits Syst. Comput., 2007)

Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths. - Qian Ding; Yu Wang 002; Hui Wang 004; Rong Luo; Huazhong Yang (ISQED, 2008)

Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection. - Fei Qiao; Huazhong Yang; Gang Huang; Hui Wang 004 (Sci. China Ser. F Inf. Sci., 2008)

Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits. - Yu Wang 002; Ku He; Rong Luo; Hui Wang 004; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Energy efficient architecture of sensor network node based on compression accelerator. - Jue Wang; Beihua Ying; Yongpan Liu; Huazhong Yang; Hui Wang 004 (ACM Great Lakes Symposium on VLSI, 2009)

A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design. - Bingbing Xia; Fei Qiao; Huazhong Yang; Hui Wang 004 (ISQED, 2010)

Lightweight Precision-Adaptive Time Synchronization in Wireless Sensor Networks. - Li Li; Yongpan Liu; Huazhong Yang; Hui Wang 004 (IEICE Trans. Commun., 2010)

Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting. - Guangming Yu; Yu Wang 002; Huazhong Yang; Hui Wang 004 (IET Circuits Devices Syst., 2010)

Output remapping technique for critical paths soft-error rate reduction. - Qian Ding; Yu Wang 002; Hui Wang 004; Rong Luo; Huazhong Yang (IET Comput. Digit. Tech., 2010)

Evaluation of Tunable Data Compression in Energy-Aware Wireless Sensor Networks. - Beihua Ying; Yongpan Liu; Huazhong Yang; Hui Wang 004 (Sensors, 2010)

Low-Power Off-Chip Memory Design for Video Decoder Using Embedded Bus-Invert Coding. - Ni Zhou; Fei Qiao; Huazhong Yang; Hui Wang 004 (ISADS, 2011)

A Low-Power IF Circuit with 5 dB Minimum Input SNR for GFSK Low-IF Receivers. - Bo Zhao 003; Guangming Yu; Tao Chen; Pengpeng Chen; Huazhong Yang; Hui Wang 004 (IEICE Trans. Electron., 2011)

A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme. - Bo Zhao 003; Huazhong Yang; Hui Wang 004 (ISCAS, 2012)

HS3DPG: Hierarchical simulation for 3D P/G network. - Shuai Tao; Xiaoming Chen 003; Yu Wang 002; Yuchun Ma; Yiyu Shi 001; Hui Wang 004; Huazhong Yang (ASP-DAC, 2013)

Superset: A Non-uniform Replica Placement Strategy towards High-Performance and Cost-Effective Distributed Storage Service. - Xiangyu Luo; Yun Wang 002; Zexi Zhang; Hui Wang 004 (CBD, 2013)

Understanding Iterative Redundancy for Vulnerability-Driven Fault Tolerance Strategy. - Hui Wang 004; Yun Wang 002; Ling Zhou; Kun Jiang (ICPCA/SWS, 2013)

Design Methodology of the Heterogeneous Multi-core Processor With the Combination of Parallelized Multi-core Simulator and Common Register File-Based Instruction Set Extension Architecture. - Bingbing Xia; Fei Qiao; Huazhong Yang; Hui Wang 004 (J. Comput., 2013)

A single channel, 6-bit 410-ms/s asynchronous SAR ADC based on 3bits/stage. - Xue Han; Nan Zhao; Qi Wei 001; Fei Qiao; Huazhong Yang; Hui Wang 004 (NEWCAS, 2014)

A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ. - Xueqing Li 002; Qi Wei 001; Zhen Xu; Jianan Liu; Hui Wang 004; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Superset: a non-uniform replica placement strategy towards perfect load balance and fine-grained power proportionality. - Xiangyu Luo; Gang Xin; Yun Wang 002; Zexi Zhang; Hui Wang 004 (Clust. Comput., 2015)

ISS: An Iterative Scrubbing Strategy for Improving Memory Reliability Against MBU. - Hui Wang 004; Yun Wang 002 (HCC, 2016)

Energy-efficient task scheduling for DVFS-enabled heterogeneous computing systems using a linear programming approach. - Yujian Zhang; Yun Wang 002; Hui Wang 004 (IPCCC, 2016)

Designing scrubbing strategy for memories suffering MCUs through the selection of optimal interleaving distance. - Wei Zhou; Hong Zhang; Hui Wang 004; Yun Wang 002 (Int. J. Comput. Sci. Eng., 2019)