Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. - Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (IWLS, 2002)

Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. - Hui-Yuan Song; S. Bohidar; R. Iris Bahar; Joel Grodstein (ICCD, 2003)

RESTA: a robust and extendable symbolic timing analysis tool. - Kundan Nepal; Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (ACM Great Lakes Symposium on VLSI, 2004)

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. - R. Iris Bahar; Hui-Yuan Song; Kundan Nepal; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Timing analysis for full-custom circuits using symbolic DC formulations. - Hui-Yuan Song; Kundan Nepal; R. Iris Bahar; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)