A novel channel estimation algorithm in OFDM power line communication system. - Huidong Zhao; Yong Hei; Shushan Qiao (ASICON, 2011)

Sentiment analysis based on transfer learning for Chinese ancient literature. - Huidong Zhao; Bin Wu 001; Haoyu Wang; Chuan Shi 001 (BESC, 2014)

A Retweet Number Prediction Model Based on Followers' Retweet Intention and Influence. - Huidong Zhao; Gang Liu 008; Chuan Shi 001; Bin Wu 001 (ICDM Workshops, 2014)

Aspect Mining with Rating Bias. - Yitong Li; Chuan Shi 001; Huidong Zhao; Fuzhen Zhuang; Bin Wu 001 (ECML/PKDD (2), 2016)

Analysis of Body Balance Indicators of the Aged based on Spatial Positions of Human Key Body Parts. - Chunsheng Hu; Huidong Zhao (CIPAE, 2020)

A fully integrated RC oscillator with adaptive-body-biasing. - Zhi Li 090; Huidong Zhao; Jialu Yin; Shushan Qiao; Yumei Zhou (IEICE Electron. Express, 2022)

A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits. - Kangning Wang 004; Huidong Zhao; Jiliang Liu; Jialu Yin; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2023)

A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM. - Pengyuan Zhao; Huidong Zhao; Jialu Yin; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2023)

A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application. - Ang Yuan; Huidong Zhao; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2023)

A 0.5V 18.6nW Bandgap Voltage Reference with A Low-Leakage Sample / Hold Circuit. - Gaigai Zhao; Zhi Li 090; Linnan Li; Zhenhao Huang; Huidong Zhao; Shushan Qiao (ICTA, 2024)

An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS. - Jiliang Liu; Huidong Zhao; Zhi Li 090; Kangning Wang 004; Shushan Qiao (IEEE Access, 2024)

An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs. - Ang Yuan; Huidong Zhao; Xiao Wang 022; Zhi Li 090; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 230-nA Quiescent Current and Enhanced Transient Performance DC-DC Converter with Suppressed Under/Overshoot for IoT SoCs. - Zhi Li 090; Huidong Zhao; Zhenhao Huang; Linnan Li; Shushan Qiao (ISCAS, 2025)

AO-EDC: An Accuracy-Oriented Error Detection and Correction Scheme for DVFS System Based on Propagation Detection at Half-Path Points. - Zitao Liang; Jiliang Liu; Kangning Wang 004; Linnan Li; Zhi Li 090; Huidong Zhao; Shushan Qiao (ISCAS, 2025)

Erratum: A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits [IEICE Electronics Express Vol. 20 (2023) No. 11 pp. 20230145]. - Kangning Wang 004; Huidong Zhao; Jiliang Liu; Jialu Yin; Zhi Li 090; Shushan Qiao (IEICE Electron. Express, 2025)

A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit. - Jiliang Liu; Huidong Zhao; Zhi Li 090; Kangning Wang 004; Shushan Qiao (IEEE Trans. Very Large Scale Integr. Syst., 2025)

ITP-PAD: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation Detection. - Kangning Wang 004; Huidong Zhao; Zhi Li 090; Jiliang Liu; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Body-Biased Hybrid Sense Amplifier With High Offset Tolerance for Low-Voltage SRAMs. - Minglong Jia; Pengyuan Zhao; Linnan Li; Xiang Li; Zhi Li 090; Huidong Zhao; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Accelerating Unstructured Sparse DNNs via Multilevel Partial Sum Reduction and PE Array-Level Load Balancing. - Chendong Xia; Qiang Li; Zhi Li 090; Bing Li 017; Huidong Zhao; Shushan Qiao (IEEE Trans. Very Large Scale Integr. Syst., 2025)