Area optimization of resilient designs guided by a mixed integer geometric program. - Hsin-Ho Huang; Huimei Cheng; Chris C. N. Chu; Peter A. Beerel (DAC, 2016)

Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs. - Yang Zhang 014; Haipeng Zha 001; Vaishnavi Sahir; Huimei Cheng; Peter A. Beerel (ASYNC, 2017)

Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems. - Huimei Cheng; Ji Li 006; Jeffrey T. Draper; Shahin Nazarian; Yanzhi Wang (ACM Great Lakes Symposium on VLSI, 2017)

Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design. - Yang Zhang 014; Huimei Cheng; Dake Chen; Huayu Fu; Shikhanshu Agarwal; Mark Lin; Peter A. Beerel (ASYNC, 2018)

Area Optimization of Timing Resilient Designs Using Resynthesis. - Hsin-Ho Huang; Huimei Cheng; Chris Chu; Peter A. Beerel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Automatic Conversion from Flip-flop to 3-phase Latch-based Designs. - Huimei Cheng; Yichen Gu; Peter A. Beerel (CoRR, 2019)

Yield modelling and analysis of bundled data and ring-oscillator based designs. - Yang Zhang 014; Ji Li 006; Huimei Cheng; Haipeng Zha 001; Jeffrey Draper; Peter A. Beerel (IET Comput. Digit. Tech., 2019)

Study on the influence of bus front-end intrusion-free distance to the bus moving characteristics. - Huimei Cheng; Huan Huang; Kai Zhang (Math. Comput. Simul., 2019)

Automatic Retiming of Two-Phase Latch-Based Resilient Circuits. - Huimei Cheng; Hsiao-Lun Wang; Minghe Zhang; Dylan Hand; Peter A. Beerel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs. - Huimei Cheng; Xi Li; Yichen Gu; Peter A. Beerel (DATE, 2020)

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol. - Sai Aparna Aketi; Smriti Gupta; Huimei Cheng; Joycee Mekie; Peter A. Beerel (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming. - Huimei Cheng; Xi Li; Yichen Gu; Peter A. Beerel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)