Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. - Ali Khaki-Firooz; Kangguo Cheng; Basanth Jagannathan; Pranita Kulkarni; Jeffrey W. Sleight; Davood Shahrjerdi; Josephine B. Chang; Sungjae Lee; Junjun Li; Huiming Bu; Robert Gauthier 002; Bruce Doris; et al. (ISSCC, 2010)

Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor. - Miaomiao Wang 006; Jingyun Zhang; Huimei Zhou; Richard G. Southwick; Robin Hsin Kuo Chao; Xin Miao; Veeraraghavan S. Basker; Tenko Yamashita; Dechao Guo; Gauri Karve; Huiming Bu; James H. Stathis (IRPS, 2019)

Backside Power Distribution for Nanosheet Technologies Beyond 2nm. - Ruilong Xie; Wonhyuk Hong; Chen Zhang; Jongjin Lee; Kevin Brew; Richard Johnson; Nicholas A. Lanzillo; Hosadurga Shobha; Taesun Kim; Panjae Park; Shogo Mochizuki; Iqbal Saraf; et al. (VLSI Technology and Circuits, 2024)