Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. - Huiyang Zhou; Matthew D. Jennings; Thomas M. Conte (LCPC, 2001)

Code Size Efficiency in Global Scheduling for ILP Processors. - Huiyang Zhou; Thomas M. Conte (Interaction between Compilers and Computer Architectures, 2002)

Detecting Global Stride Locality in Value Streams. - Huiyang Zhou; Jill Flanagan; Thomas M. Conte (ISCA, 2003)

Adaptive mode control: A static-power-efficient cache design. - Huiyang Zhou; Mark C. Toburen; Eric Rotenberg; Thomas M. Conte (ACM Trans. Embed. Comput. Syst., 2003)

Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window. - Huiyang Zhou (IEEE PACT, 2005)

Adaptive Information Processing: An Effective Way to Improve Perceptron Predictors. - Hongliang Gao; Huiyang Zhou (J. Instr. Level Parallelism, 2005)

Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. - Huiyang Zhou; Thomas M. Conte (IEEE Trans. Computers, 2005)

Improving software security via runtime instruction-level taint checking. - Jingfei Kong; Cliff Changchun Zou; Huiyang Zhou (ASID, 2006)

Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution. - Yi Ma; Huiyang Zhou (ICCD, 2006)

A case for fault tolerance and performance enhancement using chip multi-processors. - Huiyang Zhou (IEEE Comput. Archit. Lett., 2006)

Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables. - Yi Ma; Hongliang Gao; Huiyang Zhou (IEEE Trans. Computers, 2006)

Unified Architectural Support for Soft-Error Protection or Software Bug Detection. - Martin Dimitrov; Huiyang Zhou (PACT, 2007)

PMPM: Prediction by Combining Multiple Partial Matches. - Hongliang Gao; Huiyang Zhou (J. Instr. Level Parallelism, 2007)

Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery. - Yi Ma; Hongliang Gao; Martin Dimitrov; Huiyang Zhou (IEEE Trans. Parallel Distributed Syst., 2007)

Deconstructing new cache designs for thwarting software cache-based side channel attacks. - Jingfei Kong; Onur Aciiçmez; Jean-Pierre Seifert; Huiyang Zhou (CSAW, 2008)

Address-branch correlation: A novel locality for long-latency hard-to-predict branches. - Hongliang Gao; Yi Ma; Martin Dimitrov; Huiyang Zhou (HPCA, 2008)

Understanding software approaches for GPGPU reliability. - Martin Dimitrov; Mike Mantor; Huiyang Zhou (GPGPU, 2009)

Anomaly-based bug prediction, isolation, and validation: an automated approach for software debugging. - Martin Dimitrov; Huiyang Zhou (ASPLOS, 2009)

Hardware-software integrated approaches to defend against software cache-based side channel attacks. - Jingfei Kong; Onur Aciiçmez; Jean-Pierre Seifert; Huiyang Zhou (HPCA, 2009)

Accelerating MATLAB Image Processing Toolbox functions on GPUs. - Jingfei Kong; Martin Dimitrov; Yi Yang 018; Janaka Liyanage; Lin Cao; Jacob Staples; Mike Mantor; Huiyang Zhou (GPGPU, 2010)

Improving privacy and lifetime of PCM-based main memory. - Jingfei Kong; Huiyang Zhou (DSN, 2010)

A GPGPU compiler for memory optimization and parallelism management. - Yi Yang 018; Ping Xiang; Jingfei Kong; Huiyang Zhou (PLDI, 2010)

An optimizing compiler for GPGPU programs with input-data sharing. - Yi Yang 018; Ping Xiang; Jingfei Kong; Huiyang Zhou (PPoPP, 2010)

Time-Ordered Event Traces: A New Debugging Primitive for Concurrency Bugs. - Martin Dimitrov; Huiyang Zhou (IPDPS, 2011)

Combining Local and Global History for High Performance Data Prefetching. - Martin Dimitrov; Huiyang Zhou (J. Instr. Level Parallelism, 2011)

Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing. - Ping Xiang; Yi Yang 018; Mike Mantor; Norm Rubin; Huiyang Zhou (PACT, 2012)

Shared memory multiplexing: a novel way to improve GPGPU throughput. - Yi Yang 018; Ping Xiang; Mike Mantor; Norm Rubin; Huiyang Zhou (PACT, 2012)

CPU-assisted GPGPU on fused CPU-GPU architectures. - Yi Yang 018; Ping Xiang; Mike Mantor; Huiyang Zhou (HPCA, 2012)

Fixing Performance Bugs: An Empirical Study of Open-Source GPGPU Programs. - Yi Yang 018; Ping Xiang; Mike Mantor; Huiyang Zhou (ICPP, 2012)

A unified optimizing compiler framework for different GPGPU architectures. - Yi Yang 018; Ping Xiang; Jingfei Kong; Mike Mantor; Huiyang Zhou (ACM Trans. Archit. Code Optim., 2012)

Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement. - Ping Xiang; Yi Yang 018; Mike Mantor; Norm Rubin; Lisa R. Hsu; Huiyang Zhou (ICS, 2013)

Adaptive Cache Bypassing for Inclusive Last Level Caches. - Saurabh Gupta 002; Hongliang Gao; Huiyang Zhou (IPDPS, 2013)

Analyzing locality of memory references in GPU architectures. - Saurabh Gupta 002; Ping Xiang; Huiyang Zhou (MSPC@PLDI, 2013)

The Implementation of a High Performance GPGPU Compiler. - Yi Yang 018; Huiyang Zhou (Int. J. Parallel Program., 2013)

Locality principle revisited: A probability-based quantitative approach. - Saurabh Gupta 002; Ping Xiang; Yi Yang 018; Huiyang Zhou (J. Parallel Distributed Comput., 2013)

Architecting against Software Cache-Based Side-Channel Attacks. - Jingfei Kong; Onur Aciiçmez; Jean-Pierre Seifert; Huiyang Zhou (IEEE Trans. Computers, 2013)

A Highly Efficient FFT Using Shared-Memory Multiplexing. - Yi Yang 018; Huiyang Zhou (Numerical Computations with GPUs, 2014)

3D-enabled customizable embedded computer (3DECC). - Paul D. Franzon; Eric Rotenberg; James Tuck 001; Huiyang Zhou; W. Rhett Davis; Hongwen Dai; Joonmoo Huh; Sungkwan Ku; Steve Lipa; Chao Li 004; Jong Beom Park; Joshua Schabel (3DIC, 2014)

Warp-level divergence in GPUs: Characterization, impact, and mitigation. - Ping Xiang; Yi Yang 018; Huiyang Zhou (HPCA, 2014)

A Case for a Flexible Scalar Unit in SIMT Architecture. - Yi Yang 018; Ping Xiang; Michael Mantor; Norman Rubin; Lisa R. Hsu; Qunfeng Dong; Huiyang Zhou (IPDPS, 2014)

Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs. - Chao Li 004; Yi Yang 018; Hongwen Dai; Shengen Yan; Frank Mueller 001; Huiyang Zhou (ISPASS, 2014)

yaSpMV: yet another SpMV framework on GPUs. - Shengen Yan; Chao Li 004; Yunquan Zhang; Huiyang Zhou (PPoPP, 2014)

CUDA-NP: realizing nested thread-level parallelism in GPGPU applications. - Yi Yang 018; Huiyang Zhou (PPoPP, 2014)

RACB: Resource Aware Cache Bypass on GPUs. - Hongwen Dai; Christos Kartsaklis; Chao Li 004; Tomislav Janjusic; Huiyang Zhou (SBAC-PAD (Workshops), 2014)

Computing in 3D. - Paul D. Franzon; Eric Rotenberg; James Tuck 001; W. Rhett Davis; Huiyang Zhou; Joshua Schabel; Zhenqian Zhang; J. Brandon Dwiel; Elliott Forbes; Joonmoo Huh; Marcus Tshibangu; Steve Lipa (3DIC, 2015)

Revisiting ILP Designs for Throughput-Oriented GPGPU Architecture. - Ping Xiang; Yi Yang 018; Mike Mantor; Norm Rubin; Huiyang Zhou (CCGRID, 2015)

Automatic data placement into GPU on-chip memory resources. - Chao Li 004; Yi Yang 018; Zhen Lin; Huiyang Zhou (CGO, 2015)

Computing in 3D. - Paul D. Franzon; Eric Rotenberg; James Tuck 001; W. Rhett Davis; Huiyang Zhou; Joshua Schabel; Zhenqian Zhang; J. Brandon Dwiel; Elliott Forbes; Joonmoo Huh; Steve Lipa (CICC, 2015)

Spatial Locality-Aware Cache Partitioning for Effective Cache Sharing. - Saurabh Gupta 002; Huiyang Zhou (ICPP, 2015)

Locality-Driven Dynamic GPU Cache Bypassing. - Chao Li 004; Shuaiwen Leon Song; Hongwen Dai; Albert Sidelnik; Siva Kumar Sastry Hari; Huiyang Zhou (ICS, 2015)

Analyzing graphics processor unit (GPU) instruction set architectures. - Kothiya Mayank; Hongwen Dai; Jizeng Wei; Huiyang Zhou (ISPASS, 2015)

CUDA-NP: Realizing Nested Thread-Level Parallelism in GPGPU Applications. - Yi Yang 018; Chao Li 004; Huiyang Zhou (J. Comput. Sci. Technol., 2015)

OpenCL-based erasure coding on heterogeneous architectures. - Guoyang Chen; Huiyang Zhou; Xipeng Shen; Joshua Gahm; Narayan Venkat; Skip Booth; John Marshall (ASAP, 2016)

A model-driven approach to warp/thread-block level GPU cache bypassing. - Hongwen Dai; Chao Li 004; Huiyang Zhou; Saurabh Gupta 002; Christos Kartsaklis; Mike Mantor (DAC, 2016)

Tuning Stencil codes in OpenCL for FPGAs. - Qi Jia; Huiyang Zhou (ICCD, 2016)

Selectively GPU Cache Bypassing for Un-Coalesced Loads. - Chen Zhao 009; Fei Wang 008; Zhen Lin; Huiyang Zhou; Nanning Zheng 001 (ICPADS, 2016)

Optimizing memory efficiency for deep convolutional neural networks on GPUs. - Chao Li 004; Yi Yang 018; Min Feng 001; Srimat T. Chakradhar; Huiyang Zhou (SC, 2016)

Enabling efficient preemption for SIMT architectures with lightweight context switching. - Zhen Lin; Lars Nyland; Huiyang Zhou (SC, 2016)

A Cross-Platform SpMV Framework on Many-Core Architectures. - Yunquan Zhang; Shigang Li 002; Shengen Yan; Huiyang Zhou (ACM Trans. Archit. Code Optim., 2016)

POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls. - Hongwen Dai; Zhen Lin; Chao Li 004; Chen Zhao 009; Fei Wang 008; Nanning Zheng 001; Huiyang Zhou (PACT, 2017)

Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs. - Anshuman Verma; Huiyang Zhou; Skip Booth; Robbie King; James Coole; Andy Keep; John Marshall; Wu-chun Feng (DAC, 2017)

EffiSha: A Software Framework for Enabling Effficient Preemptive Scheduling of GPU. - Guoyang Chen; Yue Zhao 011; Xipeng Shen; Huiyang Zhou (PPoPP, 2017)

Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls. - Hongwen Dai; Zhen Lin; Chao Li 004; Chen Zhao 009; Fei Wang 008; Nanning Zheng 001; Huiyang Zhou (HPCA, 2018)

GPU Performance vs. Thread-Level Parallelism: Scalability Analysis and a Novel Way to Improve TLP. - Zhen Lin; Michael Mantor; Huiyang Zhou (ACM Trans. Archit. Code Optim., 2018)

Exploring Memory Persistency Models for GPUs. - Zhen Lin; Mohammad A. Alshboul; Yan Solihin; Huiyang Zhou (PACT, 2019)

Scatter-and-Gather Revisited: High-Performance Side-Channel-Resistant AES on GPUs. - Zhen Lin; Utkarsh Mathur; Huiyang Zhou (GPGPU@ASPLOS, 2019)

In-Place Zero-Space Memory Protection for CNN. - Hui Guan 001; Lin Ning 001; Zhen Lin; Xipeng Shen; Huiyang Zhou; Seung-Hwan Lim (NeurIPS, 2019)

Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation. - Huiyang Zhou; Gregory T. Byrd (IEEE Comput. Archit. Lett., 2019)

Coordinated CTA Combination and Bandwidth Partitioning for GPU Concurrent Kernel Execution. - Zhen Lin; Hongwen Dai; Michael Mantor; Huiyang Zhou (ACM Trans. Archit. Code Optim., 2019)

Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation. - Ji Liu 007; Gregory T. Byrd; Huiyang Zhou (ASPLOS, 2020)

MKPipe: a compiler framework for optimizing multi-kernel workloads in OpenCL for FPGA. - Ji Liu 007; Abdullah-Al Kafi; Xipeng Shen; Huiyang Zhou (ICS, 2020)

Reliability Modeling of NISQ- Era Quantum Computers. - Ji Liu 007; Huiyang Zhou (IISWC, 2020)

Scalable and Fast Lazy Persistency on GPUs. - Ardhi Wiratama Baskara Yudha; Keiji Kimura; Huiyang Zhou; Yan Solihin (IISWC, 2020)

Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory. - Alexander Freij; Shougang Yuan; Huiyang Zhou; Yan Solihin (MICRO, 2020)

LARQ: Learning to Ask and Rewrite Questions for Community Question Answering. - Huiyang Zhou; Haoyan Liu; Zhao Yan; Yunbo Cao; Zhoujun Li 001 (NLPCC (2), 2020)

Exploring Convolution Neural Network for Branch Prediction. - Yonghua Mao; Huiyang Zhou; Xiaolin Gui; Junjie Shen 001 (IEEE Access, 2020)

Streamlining Integrity Tree Updates for Secure Persistent Non-Volatile Memory. - Alexander Freij; Shougang Yuan; Huiyang Zhou; Yan Solihin (CoRR, 2020)

Fair and cache blocking aware warp scheduling for concurrent kernel execution on GPU. - Chen Zhao 009; Wu Gao; Feiping Nie 001; Fei Wang 008; Huiyang Zhou (Future Gener. Comput. Syst., 2020)

Relaxed Peephole Optimization: A Novel Compiler Optimization for Quantum Circuits. - Ji Liu 007; Luciano Bello; Huiyang Zhou (CGO, 2021)

PILOT: a Runtime System to Manage Multi-tenant GPU Unified Memory Footprint. - John Ravi; Tri Nguyen; Huiyang Zhou; Michela Becchi (HiPC, 2021)

Systematic Approaches for Precise and Approximate Quantum State Runtime Assertion. - Ji Liu 007; Huiyang Zhou (HPCA, 2021)

PSSM: achieving secure memory for GPUs with partitioned and sectored security metadata. - Shougang Yuan; Yan Solihin; Huiyang Zhou (ICS, 2021)

Message from the Program Chairs. - Tim Rogers; Huiyang Zhou (IISWC, 2021)

Analyzing Secure Memory Architecture for GPUs. - Shougang Yuan; Ardhi Wiratama Baskara Yudha; Yan Solihin; Huiyang Zhou (ISPASS, 2021)

Bonsai Merkle Forests: Efficiently Achieving Crash Consistency in Secure Persistent Memory. - Alexander Freij; Huiyang Zhou; Yan Solihin (MICRO, 2021)

Not All SWAPs Have the Same Cost: A Case for Optimization-Aware Qubit Routing. - Ji Liu 007; Peiyi Li 002; Huiyang Zhou (HPCA, 2022)

Adaptive Security Support for Heterogeneous Memory on GPUs. - Shougang Yuan; Amro Awad; Ardhi Wiratama Baskara Yudha; Yan Solihin; Huiyang Zhou (HPCA, 2022)

Exploiting Quantum Assertions for Error Mitigation and Quantum Program Debugging. - Peiyi Li 002; Ji Liu 007; Yangjia Li; Huiyang Zhou (ICCD, 2022)

LITE: a low-cost practical inter-operable GPU TEE. - Ardhi Wiratama Baskara Yudha; Jake Meyer; Shougang Yuan; Huiyang Zhou; Yan Solihin (ICS, 2022)

Deep Learning based Data Prefetching in CPU-GPU Unified Virtual Memory. - Xinjian Long; Xiangyang Gong; Huiyang Zhou (CoRR, 2022)

An Intelligent Framework for Oversubscription Management in CPU-GPU Unified Memory. - Xinjian Long; Xiangyang Gong; Huiyang Zhou (CoRR, 2022)

A Survey of GPU Multitasking Methods Supported by Hardware Architecture. - Chen Zhao 009; Wu Gao; Feiping Nie 001; Huiyang Zhou (IEEE Trans. Parallel Distributed Syst., 2022)

Plutus: Bandwidth-Efficient Memory Security for GPUs. - Rahaf Abdullah; Huiyang Zhou; Amro Awad (HPCA, 2023)

SecPB: Architectures for Secure Non-Volatile Memory with Battery-Backed Persist Buffers. - Alexander Freij; Huiyang Zhou; Yan Solihin (HPCA, 2023)

Enhancing Virtual Distillation with Circuit Cutting for Quantum Error Mitigation. - Peiyi Li 002; Ji Liu 007; Hrushikesh Pramod Patil; Paul D. Hovland; Huiyang Zhou (ICCD, 2023)

PBVR: Physically Based Rendering in Virtual Reality. - Yavuz Selim Tozlu; Huiyang Zhou (IISWC, 2023)

Folding-Free ZNE: A Comprehensive Quantum Zero-Noise Extrapolation Approach for Mitigating Depolarizing and Decoherence Noise. - Hrushikesh Pramod Patil; Peiyi Li 002; Ji Liu 007; Huiyang Zhou (QCE, 2023)

An Intelligent Framework for Oversubscription Management in CPU-GPU Unified Memory. - Xinjian Long; Xiangyang Gong; Bo Zhang 032; Huiyang Zhou (J. Grid Comput., 2023)

Deep learning based data prefetching in CPU-GPU unified virtual memory. - Xinjian Long; Xiangyang Gong; Bo Zhang 032; Huiyang Zhou (J. Parallel Distributed Comput., 2023)

BoostCom: Towards Efficient Universal Fully Homomorphic Encryption by Boosting the Word-wise Comparisons. - Ardhi Wiratama Baskara Yudha; Jiaqi Xue; Qian Lou; Huiyang Zhou; Yan Solihin (PACT, 2024)

Salus: Efficient Security Support for CXL-Expanded GPU Memory. - Rahaf Abdullah; Hyokeun Lee; Huiyang Zhou; Amro Awad (HPCA, 2024)

Tetris: A Compilation Framework for VQA Applications in Quantum Computing. - Yuwei Jin; Zirui Li; Fei Hua; Tianyi Hao 003; Huiyang Zhou; Yipeng Huang 001; Eddy Z. Zhang (ISCA, 2024)

QuTracer: Mitigating Quantum Gate and Measurement Errors by Tracing Subsets of Qubits. - Peiyi Li 002; Ji Liu 007; Alvin Gonzales; Zain H. Saleem; Huiyang Zhou; Paul D. Hovland (ISCA, 2024)

SEFsim: A Statistically-Guided Fast DRAM Simulator. - Debpratim Adak; Hyokeun Lee; Ben Feinberg; Gwendolyn Voskuilen; Clayton Hughes; Huiyang Zhou; Amro Awad (ISPASS, 2024)

Qubit-Wise Majority Vote: Maximum Likelihood Quantum Error Mitigation for Algorithms with a Single Correct Output. - Dror Baron; Hrushikesh Pramod Patil; Huiyang Zhou (QCE, 2024)

Posters Program: 2024 IEEE International Conference on Quantum Computing and Engineering. - Fan Chen 001; Huiyang Zhou (QCE, 2024)

Dynamic Runtime Assertions in Quantum Ternary Systems. - Ehsan Faghih; Huiyang Zhou (QCE, 2024)

Error Mitigation of Hamiltonian Simulations from an Analog-Based Compiler (SimuQ). - Amey Meher; Yuan Liu; Huiyang Zhou (QCE, 2024)

Understanding Error Sensitivity of Quantum Circuits. - Shubdeep Mohapatra; Huiyang Zhou (QCE, 2024)

Maximum Likelihood Quantum Error Mitigation for Algorithms with a Single Correct Output. - Dror Baron; Hrushikesh Pramod Patil; Huiyang Zhou (CoRR, 2024)

SpecMPK: Efficient In-Process Isolation with Speculative and Secure Permission Update Instruction. - Debpratim Adak; Huiyang Zhou; Eric Rotenberg; Amro Awad (HPCA, 2025)

Genesis: A Compiler for Hamiltonian Simulation on Hybrid CV-DV Quantum Computers. - Zihan Chen 005; Jiakang Li; Minghao Guo; Henry Chen; Zirui Li; Joel Bierman; Yipeng Huang 001; Huiyang Zhou; Yuan Liu; Eddy Z. Zhang (ISCA, 2025)

CoopRT: Accelerating BVH Traversal for Ray Tracing via Cooperative Threads. - Yavuz Selim Tozlu; Huiyang Zhou (ISCA, 2025)

Delta Counter: Bandwidth-Efficient Encryption Counter Representation for Secure GPU Memory. - Shougang Yuan; Amro Awad; Huiyang Zhou (IEEE Trans. Dependable Secur. Comput., 2025)

Genesis: A Compiler Framework for Hamiltonian Simulation on Hybrid CV-DV Quantum Computers. - Zihan Chen 005; Jiakang Li; Minghao Guo; Henry Chen; Zirui Li; Joel Bierman; Yipeng Huang 001; Huiyang Zhou; Yuan Liu; Eddy Z. Zhang (CoRR, 2025)