Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs. - Kyeong-Sik Min; Hun-Dae Choi; H.-Y. Choi; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A 1.06V 5Gb/s/pin 16Gb LPDDR4x DRAM Adopting Sense Amplifier with AC-Coupled Equalizer, Stacked Output Driver, and Clock MUX with Inverter-Based Transmission Gate for Mobile and Automotive Application. - Young-Gil Go; Hyun-A. Ahn; Yoo-Chang Sung; Myung-Hun Jung; Ji-Geon Yeom; Hun-Dae Choi; Janghoo Kim; Hyunjin Ko; Miyoung Woo; Seong-O. Huh; Seung-Jun Bae; Tae-Young Oh (A-SSCC, 2024)