A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. - Kyomin Sohn; Taesik Na; Indal Song; Yong Shim; Wonil Bae; Sanghee Kang; Dongsu Lee; Hangyun Jung; Hanki Jeoung; Ki Won Lee; Junsuk Park; Jongeun Lee; et al. (ISSCC, 2012)

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. - Kyomin Sohn; Taesik Na; Indal Song; Yong Shim; Wonil Bae; Sanghee Kang; Dongsu Lee; Hangyun Jung; Seok-Hun Hyun; Hanki Jeoung; Ki Won Lee; Jun-Seok Park; et al. (IEEE J. Solid State Circuits, 2013)

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs. - Reum Oh; Byunghyun Lee; Sang-Woong Shin; Wonil Bae; Hundai Choi; Indal Song; Yun-Sang Lee; Jung-Hwan Choi; Chi-Wook Kim; Seong-Jin Jang; Joo-Sun Choi (VLSIC, 2014)

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs. - Won-Joo Yun; Indal Song; Hanki Jeoung; Hundai Choi; Seok-Ho Lee; Jun-Bae Kim; Chi-Wook Kim; Jung-Hwan Choi; Seong-Jin Jang; Joo-Sun Choi (ISSCC, 2015)

An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM. - Joung-Wook Moon; Hye-Sung Yoo; Hundai Choi; Il-Won Park; Seok-Yong Kang; Jun-Bae Kim; Haeyoung Chung; Kiho Kim; Dong-Hun Lee; Ki-Jae Song; Seok-Hun Hyun; Indal Song; et al. (A-SSCC, 2018)