Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. - Hung-Chang Yu; Kai-Chun Lin; Ku-Feng Lin; Chin-Yi Huang; Yu-Der Chih; Tong-Chern Ong; Tsung-Yung Jonathan Chang; Sreedhar Natarajan; Luan C. Tran (ISSCC, 2013)

A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V. - Hung-Chang Yu; Ku-Feng Lin; Kai-Chun Lin; Yu-Der Chih; Sreedhar Natarajan (VLSI-DAT, 2013)

Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2018)

Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $ mu$ A Sensing Resolution, and 17.5-nS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2019)

User-centered empathy design: a prototype of school-age children learning aids system. - Hung-Chang Yu; C.-J. Chou; Ding-Bang Luh; Ming-Hsuan Hsieh (J. Ambient Intell. Humaniz. Comput., 2023)