Redundancy check technique for designing optimal networks by branch-and-bound method. - Hung Chi Lai; Tomoyasu Nakagawa; Saburo Muroga (Int. J. Parallel Program., 1974)

Minimization of Logic Networks Under a Generalized Cost Function. - Saburo Muroga; Hung Chi Lai (IEEE Trans. Computers, 1976)

A Study of Current Logic Design Problems: Part I, Design of Diagnosable Mos Networks; Part Ii, Minimum Nor (Nand) Networks for Parity Functions of an Arbitrary Number of Variables; Part Iii, Minimum Parallel Binary Adders With Nor (Nand) Gates and Their Extensions to Networks Consisting of Carry-Save Adders - Hung Chi Lai (1976)

Minimum Parallel Binary Adders with NOR (NAND) Gates. - Hung Chi Lai; Saburo Muroga (IEEE Trans. Computers, 1979)

Logic Networks of Carry-Save Adders. - Hung Chi Lai; Saburo Muroga (IEEE Trans. Computers, 1982)

Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables. - Hung Chi Lai; Saburo Muroga (IEEE Trans. Computers, 1987)

Design of MOS networks in single-rail input logic for incompletely specified functions. - Hung Chi Lai; Saburo Muroga (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

The Transduction Method-Design of Logic Networks Based on Permissible Functions. - Saburo Muroga; Yahiko Kambayashi; Hung Chi Lai; Jay Niel Culliney (IEEE Trans. Computers, 1989)

Energy Efficiency Power Control of Cell Breathing in EPON-WiMAX Hybrid Access Network. - Hung-Yi Teng; Hung Chi Lai; Ren-Hung Hwang (J. Interconnect. Networks, 2012)