Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation. - Shen-Fu Hsiao; Jian-Ming Chen; Yu-Hong Chen; Hung-Ching Li; Yi Hsu (ISCAS, 2021)

Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination. - Shen-Fu Hsiao; Hung-Ching Li; Yu-Che Yen; Po-Chang Li (ISCAS, 2022)