etection of SRAM cell stability by lowering array supply voltage. - Ding-Ming Kwai; Hung-Wen Chang; Hung-Jen Liao; Ching-Hua Chiao; Yung-Fa Chou (Asian Test Symposium, 2000)

A 45nm dual-port SRAM with write and read capability enhancement at low voltage. - D. P. Wang; Hung-Jen Liao; Hiroyuki Yamauchi; Y. H. Chen; Y. L. Lin; S. H. Lin; D. C. Liu; Huan-Cheng Chang; W. Hwang (SoCC, 2007)

A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. - Yen-Huei Chen; Gary Chan; Shao-Yu Chou; Hsien-Yu Pan; Jui-Jen Wu; Robin Lee; Hung-Jen Liao; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2009)

A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications. - Meng-Fan Chang; Jui-Jen Wu; Kuang-Ting Chen; Yung-Chi Chen; Yen-Hui Chen; Robin Lee; Hung-Jen Liao; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2010)

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Shang-Chi Wu; Chia-En Huang; Han-Chao Lai; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; et al. (ISSCC, 2011)

A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme. - Jui-Jen Wu; Yen-Hui Chen; Meng-Fan Chang; Po-Wei Chou; Chien-Yuan Chen; Hung-Jen Liao; Ming-Bin Chen; Yuan-Hua Chu; Wen-Chin Wu; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2011)

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM. - Yen-Huei Chen; Shao-Yu Chou; Quincy Li; Wei-Min Chan; Dar Sun; Hung-Jen Liao; Ping Wang; Meng-Fan Chang; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2012)

A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications. - Jonathan Chang; Yen-Huei Chen; Hank Cheng; Wei-Min Chan; Hung-Jen Liao; Quincy Li; Stanley Chang; Sreedhar Natarajan; Robin Lee; Ping-Wei Wang; Shyue-Shyh Lin; Chung-Cheng Wu; et al. (ISSCC, 2013)

Intrusion detection system: A comprehensive review. - Hung-Jen Liao; Chun-Hung Richard Lin; Ying-Chih Lin; Kuang-Yuan Tung (J. Netw. Comput. Appl., 2013)

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2013)

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS. - Ching-Wei Wu; Ming-Hung Chang; Chia-Cheng Chen; Robin Lee; Hung-Jen Liao; Jonathan Chang (A-SSCC, 2014)

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. - Yen-Huei Chen; Wei-Min Chan; Wei-Cheng Wu; Hung-Jen Liao; Kuo-Hua Pan; Jhon-Jhy Liaw; Tang-Hsuan Chung; Quincy Li; George H. Chang; Chih-Yung Lin; Mu-Chi Chiang; Shien-Yang Wu; et al. (ISSCC, 2014)

The importance of DFX, a foundry perspective. - Saman Adham; Jonathan Chang; Hung-Jen Liao; John Hung; Ting-Hua Hsieh (ITC, 2014)

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies. - Hidehiro Fujiwara; Li-Wen Wang; Yen-Huei Chen; Kao-Cheng Lin; Dar Sun; Shin-Rung Wu; Jhon-Jhy Liaw; Chih-Yung Lin; Mu-Chi Chiang; Hung-Jen Liao; Shien-Yang Wu; Jonathan Chang (ISSCC, 2015)

A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. - Yen-Huei Chen; Wei-Min Chan; Wei-Cheng Wu; Hung-Jen Liao; Kuo-Hua Pan; Jhon-Jhy Liaw; Tang-Hsuan Chung; Quincy Li; Chih-Yung Lin; Mu-Chi Chiang; Shien-Yang Wu; Jonathan Chang (IEEE J. Solid State Circuits, 2015)

A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications. - Hidehiro Fujiwara; Yen-Huei Chen; Chih-Yu Lin; Wei-Cheng Wu; Dar Sun; Shin-Rung Wu; Hung-Jen Liao; Jonathan Chang (A-SSCC, 2016)

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications. - Yen-Huei Chen; Kao-Cheng Lin; Ching-Wei Wu; Wei-Min Chan; Jhon-Jhy Liaw; Hung-Jen Liao; Jonathan Chang (VLSI Circuits, 2016)

An efficient tabu search for cell planning problem in mobile communication. - Chun-Hung Richard Lin; Hung-Jen Liao; Ying-Chih Lin; Jain-Shing Liu; Yu-Hsiu Huang (Wirel. Commun. Mob. Comput., 2016)

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. - Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Sahil Preet Singh; Hank Cheng; Hidehiro Fujiwara; Jih-Yu Lin; Kao-Cheng Lin; John Hung; Robin Lee; Hung-Jen Liao; Jhon-Jhy Liaw; et al. (ISSCC, 2017)

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications. - Michael Clinton; Hank Cheng; Hung-Jen Liao; Robin Lee; Ching-Wei Wu; Johnny Yang; Hau-Tai Hsieh; Frank Wu; Jung-Ping Yang; Atul Katoch; Arun Achyuthan; Donald Mikan; et al. (ISSCC, 2017)

A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology. - Mahmut E. Sinangil; Yen-Ting Lin; Hung-Jen Liao; Jonathan Chang (VLSI Circuits, 2018)

A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. - Hidehiro Fujiwara; Chih-Yu Lin; Hsien-Yu Pan; Cheng-Han Lin; Po-Yi Huang; Kao-Cheng Lin; Jhon-Jhy Liaw; Yen-Huei Chen; Hung-Jen Liao; Jonathan Chang (ISSCC, 2019)

A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell. - Mahmut E. Sinangil; Yen-Ting Lin; Hung-Jen Liao; Jonathan Chang (IEEE J. Solid State Circuits, 2019)

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. - Qing Dong 001; Mahmut E. Sinangil; Burak Erbagci; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang (ISSCC, 2020)

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (ISSCC, 2020)

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. - Yu-Der Chih; Po-Hao Lee; Hidehiro Fujiwara; Yi-Chun Shih; Chia-Fu Lee; Rawan Naous; Yu-Lin Chen; Chieh-Pu Lo; Cheng-Han Lu; Haruki Mori; Wei-Cheng Zhao; Dar Sun; et al. (ISSCC, 2021)

A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue. - Hidehiro Fujiwara; Yi-Hsin Nien; Chih-Yu Lin; Hsien-Yu Pan; Hao-Wen Hsu; Shin-Rung Wu; Yao-Yi Liu; Yen-Huei Chen; Hung-Jen Liao; Jonathan Chang (ISSCC, 2021)

3D-printed mold-assisted U-shaped optical fiber sensor for displacement sensing. - Hung-Jen Liao; Chin-Ping Yu (WOCC, 2021)

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (IEEE J. Solid State Circuits, 2021)

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. - Mahmut E. Sinangil; Burak Erbagci; Rawan Naous; Kerem Akarvardar; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang (IEEE J. Solid State Circuits, 2021)

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Mei-Chen Chuang; Rawan Naous; Chao-Kai Chuang; Takeshi Hashizume; Dar Sun; Chia-Fu Lee; Kerem Akarvardar; Saman Adham; Tan-Li Chou; et al. (ISSCC, 2022)

A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology. - Nail Etkin Can Akkaya; Gary Chan; Hung-Jen Liao; Yih Wang; Jonathan Chang (VLSI Technology and Circuits, 2022)

A 4nm 6163-TOPS/W/b $ mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. - Haruki Mori; Wei-Chang Zhao; Cheng-En Lee; Chia-Fu Lee; Yu-Hao Hsu; Chao-Kai Chuang; Takeshi Hashizume; Hao-Chun Tung; Yao-Yi Liu; Shin-Rung Wu; Kerem Akarvardar; Tan-Li Chou; et al. (ISSCC, 2023)

A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. - Yumito Aoyagi; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Sevic Chen; Peijiun Lin; Ching-Wei Wu; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; et al. (VLSI Technology and Circuits, 2023)

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. - Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Jhon-Jhy Liaw; Shien-Yang Michael Wu; Quincy Li; Hidehiro Fujiwara; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology. - Nick Zhang; Young Suk Kim; Peter Hsu; Samsoo Kim; Derek Tao; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Kinshuk Khare; Cheng-En Lee; Xiaochen Peng; Vineet Joshi; Chao-Kai Chuang; Shu-Huan Hsu; Takeshi Hashizume; Toshiaki Naganuma; Chen-Hung Tien; et al. (ISSCC, 2024)

A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. - Ming-Chieh Huang; Wei Wing Mar; Shankar Kanade; Boris Bai; Aditya Gayatri; Krishna Khairnar; Amy Lai; Yu-Hao Hsu; Hung-Jen Liao; Yih Wang; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. - Tomotaka Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Yumito Aoyagi; Masaya Hamada; Kazuto Mizutani; Koji Nii; Hidehiro Fujiwara; Isabel Wang; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. - Yumito Aoyagi; Koji Nii; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2024)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)

29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme. - Hidehiro Fujiwara; Wei-Chang Zhao; Kinshuk Khare; Yi-Hsin Nien; Chih-Yu Lin; Cheng-Han Lin; Shan-Ru Liao; Kenta Torigoe; Shirleen Xia; Yuichiro Ishii; Yao-Yi Lin; Jhon-Jhy Liaw; et al. (ISSCC, 2025)

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications. - Yoshiaki Osada; Takaaki Nakazato; Yumito Aoyagi; Koji Nii; Jhon-Jhy Liaw; Shien-Yang Wu; Quincy Li; Hidehiro Fujiwara; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)