Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip. - Hung K. Nguyen; Peng Cao 002; Xuexiang Wang; Jun Yang 006; Longxing Shi; Min Zhu 001; Leibo Liu; Shaojun Wei (IEICE Trans. Inf. Syst., 2013)

A novel priority-driven arbiter for the router in reconfigurable Network-on-Chips. - Hung K. Nguyen; Xuan-Tu Tran (ICICDT, 2018)

A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications. - Pham-Khoi Dong; Hung K. Nguyen; Xuan-Tu Tran (ISCIT, 2019)

A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs. - Hung K. Nguyen; Xuan-Tu Tran (J. Syst. Archit., 2019)

Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture. - Pham-Khoi Dong; Hung K. Nguyen; Van-Phuc Hoang; Xuan-Tu Tran (APCCAS, 2020)

Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks. - Xuan-Tu Tran; Ngoc-Sinh Nguyen; Duy-Hieu Bui; Minh-Trien Pham; Hung K. Nguyen; Cong-Kha Pham (EAI Endorsed Trans. Ind. Networks Intell. Syst., 2020)

A Low-cost High-performance 2D-Convolution Accelerator for Deep Neural Networks in IoT. - Hung K. Nguyen; Anh T. Nguyen (RIVF, 2022)

Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator. - Hung K. Nguyen; Xuan-Tu Tran (ACM Trans. Parallel Comput., 2022)

RTL Design of an Accelerator for Softmax Layer in Deep Neural Networks. - Quyen V. Hoang; Hung K. Nguyen (RIVF, 2024)

Developing a Deep Learning-Based Embedded System to Detect Adverse Weather Conditions for Autonomous Vehicles. - Khanh-Van H. Ngo; Hung K. Nguyen (RIVF, 2024)