尋易（Csmart-Ⅱ）：智慧型網路中文資訊檢索系統 (An Intelligent Chinese Information Retrieval System for the Internet) [In Chinese]. - Lee-Feng Chien; Ming-Jer Lee; Ming-Chuan Chen; Hung-Ming Chen; Ting-Chi Chen; Wei-Feng Tung; Hung-Chung Lee; Duen-Yi Huang; Yuan-Cheng Chang (ROCLING, 1996)

Integrated floorplanning and interconnect planning. - Hung-Ming Chen; Hai Zhou 001; Fung Yu Young; D. F. Wong 001; Hannah Honghua Yang; Naveed A. Sherwani (ICCAD, 1999)

Integrated power supply planning and floorplanning. - I-Min Liu; Hung-Ming Chen; Tan-Li Chou; Adnan Aziz; D. F. Wong 001 (ASP-DAC, 2001)

Faster and more accurate wiring evaluation in interconnect-centric floorplanning. - Hung-Ming Chen; D. F. Wong 001; Wai-Kei Mak; Hannah Honghua Yang (ACM Great Lakes Symposium on VLSI, 2001)

Floorplanning with power supply noise avoidance. - Hung-Ming Chen; Li-Da Huang; I-Min Liu; Minghorng Lai; D. F. Wong 001 (ASP-DAC, 2003)

Global Wire Bus Configuration with Minimum Delay Uncertainty. - Li-Da Huang; Hung-Ming Chen; D. F. Wong 001 (DATE, 2003)

Designing platform-based system power management on a smart tablet appliance. - Hung-Ming Chen; Po-Hung Chen; Tai-Jee Pan; Feipei Lai (ICECS, 2003)

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. - Hung-Ming Chen; I-Min Liu; Martin D. F. Wong; Muzhou Shao; Li-Da Huang (ICCD, 2004)

Design of Nearest Neighbor Classifiers Using an Intelligent Multi-objective Evolutionary Algorithm. - Jian-Hung Chen; Hung-Ming Chen; Shinn-Ying Ho (PRICAI, 2004)

Design of accurate classifiers with a compact fuzzy-rule base using an evolutionary scatter partition of feature space. - Shinn-Ying Ho; Hung-Ming Chen; Shinn-Jang Ho; Tai-Kang Chen (IEEE Trans. Syst. Man Cybern. Part B, 2004)

Efficient gene selection for classification of microarray data. - Shinn-Ying Ho; Chong-Cheng Lee; Hung-Ming Chen; Hui-Ling Huang (Congress on Evolutionary Computation, 2005)

Flexible protein-ligand docking using particle swarm optimization. - Bo-Fu Liu; Hung-Ming Chen; Hui-Ling Huang; Shiow-Fen Hwang; Shinn-Ying Ho (Congress on Evolutionary Computation, 2005)

MeSwarm: memetic particle swarm optimization. - Bo-Fu Liu; Hung-Ming Chen; Jian-Hung Chen; Shiow-Fen Hwang; Shinn-Ying Ho (GECCO, 2005)

Current Calculation on VLSI Signal Interconnects. - Muzhou Shao; Youxin Gao; Li-Pen Yuan; Hung-Ming Chen; Martin D. F. Wong (ISQED, 2005)

Design of nearest neighbor classifiers: multi-objective approach. - Jian-Hung Chen; Hung-Ming Chen; Shinn-Ying Ho (Int. J. Approx. Reason., 2005)

Simultaneous power supply planning and noise avoidance in floorplan design. - Hung-Ming Chen; Li-Da Huang; I-Min Liu; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design. - Li-Chung Hsu; Hung-Ming Chen (ISQED, 2006)

Scoring Method for Tumor Prediction from Microarray Data Using an Evolutionary Fuzzy Classifier. - Shinn-Ying Ho; Chih-Hung Hsieh; Kuan-Wei Chen; Hui-Ling Huang; Hung-Ming Chen; Shinn-Jang Ho (PAKDD, 2006)

On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study. - Huang-Liang Chen; Hung-Ming Chen (SoCC, 2006)

Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. - Ming-Ching Lu; Meng-Chen Wu; Hung-Ming Chen; Iris Hui-Ru Jiang (SoCC, 2006)

Markov model fuzzy-reasoning based algorithm for fast block motion estimation. - Po-Hung Chen; Hung-Ming Chen; Kuo-Jui Hung; Wen-Hsien Fang; Mon-Chau Shie; Feipei Lai (J. Vis. Commun. Image Represent., 2006)

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. - Hung-Ming Chen; I-Min Liu; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. - Ren-Jie Lee; Ming-Fang Lai; Hung-Ming Chen (ASP-DAC, 2007)

On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu (ASP-DAC, 2007)

A selective pattern-compression scheme for power and test-data reduction. - Chia-Yi Lin; Hung-Ming Chen (ICCAD, 2007)

Using power gating techniques in area-array SoC floorplan design. - Chi-Yi Yeh; Hung-Ming Chen; Li-Da Huang; Wei-Ting Wei; Chao-Hung Lu; Chien-Nan Jimmy Liu (SoCC, 2007)

Accurate prediction of enzyme subfamily class using an adaptive fuzzy k-nearest neighbor method. - Wen-Lin Huang; Hung-Ming Chen; Shiow-Fen Hwang; Shinn-Ying Ho (Biosyst., 2007)

Center of Mass-Based Adaptive Fast Block Motion Estimation. - Hung-Ming Chen; Po-Hung Chen; Kuo-Liang Yeh; Wen-Hsien Fang; Mon-Chau Shie; Feipei Lai (EURASIP J. Image Video Process., 2007)

SODOCK: Swarm optimization for highly flexible protein-ligand docking. - Hung-Ming Chen; Bo-Fu Liu; Hui-Ling Huang; Shiow-Fen Hwang; Shinn-Ying Ho (J. Comput. Chem., 2007)

Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow. - Lun-Chun Wei; Hung-Ming Chen; Li-Da Huang; Sarah Songjie Xu (ACM Great Lakes Symposium on VLSI, 2008)

Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations. - Bruce Tseng; Hung-Ming Chen (ISPD, 2008)

An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign. - Ming-Fang Lai; Hung-Ming Chen (ISQED, 2008)

Web-FEM: An internet-based finite-element analysis framework with 3D graphics and parallel computing environment. - Hung-Ming Chen; Yu-Chin Lin (Adv. Eng. Softw., 2008)

An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu (J. Inf. Sci. Eng., 2008)

Effective decap insertion in area-array SoC floorplan design. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu (ACM Trans. Design Autom. Electr. Syst., 2008)

Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization. - Chia-Yi Chang; Hung-Ming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu; Wen-Yu Shih (DATE, 2009)

A stochastic-based efficient critical area extractor on OpenAccess platform. - Bo-Zhou Chen; Hung-Ming Chen; Li-Da Huang; Po-Cheng Pan (ACM Great Lakes Symposium on VLSI, 2009)

Buffer/flip-flop block planning for power-integrity-driven floorplanning. - Hsin-Hua Pan; Hung-Ming Chen; Chia-Yi Chang (ISQED, 2009)

Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. - Meng-Chen Wu; Ming-Ching Lu; Hung-Ming Chen; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2009)

Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign. - Ren-Jie Lee; Hung-Ming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Technology mapping with crosstalk noise avoidance. - Fang-Yu Fan; Hung-Ming Chen; I-Min Liu (ASP-DAC, 2010)

A novel two-dimensional scan-control scheme for test-cost reduction. - Chia-Yi Lin; Hung-Ming Chen (ISQED, 2010)

Simultaneous voltage island generation and floorplanning. - Houng-Yi Li; Iris Hui-Ru Jiang; Hung-Ming Chen (SoCC, 2010)

Image Enlargement by Applying Coordinate Rotation and Kernel Stretching to Interpolation Kernels. - Sheng-Fu Liang; Hung-Ming Chen; Yi-Che Liu (EURASIP J. Adv. Signal Process., 2010)

On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques. - Chia-Yi Lin; Li-Chung Hsu; Hung-Ming Chen (IEICE Trans. Electron., 2010)

On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes. - Chia-Yi Lin; Hsiu-Chuan Lin; Hung-Ming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Row-based area-array I/O design planning in concurrent chip-package design flow. - Ren-Jie Lee; Hung-Ming Chen (ASP-DAC, 2011)

On routing fixed escaped boundary pins for high speed boards. - Tsung-Ying Tsai; Ren-Jie Lee; Ching-Yu Chin; Chung-Yi Kuan; Hung-Ming Chen; Yoji Kajitani (DATE, 2011)

Fast analog layout prototyping for nanometer design migration. - Yi-Peng Weng; Hung-Ming Chen; Tung-Chieh Chen; Po-Cheng Pan; Chien-Hung Chen; Wei-Zen Chen (ICCAD, 2011)

The Development of Smart Assistive Technology Devices for Urinary Catheterization Monitoring. - Chuan-Pin Lu; Jui-Pin Li; Wei-Yi Liou; Hung-Ming Chen (ICGEC, 2011)

Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping. - Kuo-Hsuan Meng; Po-Cheng Pan; Hung-Ming Chen (ISQED, 2011)

Clock planning for multi-voltage and multi-mode designs. - Chang-Cheng Tsai; Tzu-Hen Lin; Shin-Han Tsai; Hung-Ming Chen (ISQED, 2011)

Mixed non-rectangular block packing for non-Manhattan layout architectures. - Meng-Chen Wu; Hung-Ming Chen; Jing-Yang Jou (ISQED, 2011)

New Sorting Technique on Partial Distortion Search Using Two Bit-Transform for Fast Optimal Motion Estimation. - Hung-Ming Chen; Po-Hung Chen; Jian-Hong Ciou (RVSP, 2011)

TSV-based 3D-IC placement for timing optimization. - Yi-Rong Chen; Hung-Ming Chen; Shih-Ying Liu (SoCC, 2011)

Aseismic ability estimation of school building using predictive data mining models. - Wei-Ko Kao; Hung-Ming Chen; Jui-Sheng Chou (Expert Syst. Appl., 2011)

A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost Reduction. - Chia-Yi Lin; Hung-Ming Chen (J. Inf. Sci. Eng., 2011)

Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu (J. Inf. Sci. Eng., 2011)

Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign. - Ren-Jie Lee; Hung-Ming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A fast thermal aware placement with accurate thermal analysis based on Green function. - Suradeth Aroonsantidecha; Shih-Ying Liu; Ching-Yu Chin; Hung-Ming Chen (ASP-DAC, 2012)

On effective flip-chip routing via pseudo single redistribution layer. - Hsin-Wu Hsu; Meng-Ling Chen; Hung-Ming Chen; Hung-Chun Li; Shi-Hao Chen (DATE, 2012)

Agglomerative-based flip-flop merging with signal wirelength optimization. - Shih-Ying Liu; Chieh-Jui Lee; Hung-Ming Chen (DATE, 2012)

Configurable analog routing methodology via technology and design constraint unification. - Po-Cheng Pan; Hung-Ming Chen; Yi-Kan Cheng; Jill Liu; Wei-Yi Hu (ICCAD, 2012)

On construction low power and robust clock tree via slew budgeting. - Yeh-Chi Chang; Chun-Kai Wang; Hung-Ming Chen (ISPD, 2012)

Hierarchical power network synthesis for multiple power domain designs. - Chieh-Jui Lee; Shih-Ying Liu; Chuan-Chia Huang; Hung-Ming Chen; Chang-Tzu Lin; Chia-Hsin Lee (ISQED, 2012)

K-means particle swarm optimization with embedded chaotic search for solving multidimensional problems. - Min-Yuan Cheng; Kuo-Yu Huang; Hung-Ming Chen (Appl. Math. Comput., 2012)

Genetic programming for predicting aseismic abilities of school buildings. - Hung-Ming Chen; Wei-Ko Kao; Hsing-Chih Tsai (Eng. Appl. Artif. Intell., 2012)

An Efficient and Secure Dynamic ID-based Authentication Scheme for Telecare Medical Information Systems. - Hung-Ming Chen; Jung-Wen Lo; Chang-Kuo Yeh (J. Medical Syst., 2012)

Dynamic guiding particle swarm optimization with embedded chaotic search for solving multidimensional problems. - Min-Yuan Cheng; Kuo-Yu Huang; Hung-Ming Chen (Optim. Lett., 2012)

A network-flow based algorithm for power density mitigation at post-placement stage. - Shih-Ying Sean Liu; Ren-Guo Luo; Hung-Ming Chen (DATE, 2013)

Effective power network prototyping via statistical-based clustering and sequential linear programming. - Shih-Ying Sean Liu; Chieh-Jui Lee; Chuan-Chia Huang; Hung-Ming Chen; Chang-Tzu Lin; Chia-Hsin Lee (DATE, 2013)

PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design. - Po-Cheng Pan; Hung-Ming Chen; Chien-Chih Lin (DATE, 2013)

Efficient analog layout prototyping by layout reuse with routing preservation. - Ching-Yu Chin; Po-Cheng Pan; Hung-Ming Chen; Tung-Chieh Chen; Jou-Chun Lin (ICCAD, 2013)

A fuzzy thresholding early termination scheme of fast motion estimation for video coding. - Hung-Ming Chen; Jhong-Kai Lin; Po-Hung Chen; Ting-Jhao Jheng (ISCE, 2013)

Design of mobile healthcare service with health records format evaluation. - Hung-Ming Chen; Yong-Zan Liou; Shih-Ying Chen; Jhuo-Syun Li (ISCE, 2013)

On the way to practical tools for beyond die codesign and integration. - Hung-Ming Chen (ISPD, 2013)

Using MapReduce Framework for Mining Association Rules. - Shih-Ying Chen; Jia-Hong Li; Ke-Chung Lin; Hung-Ming Chen; Tung-Shou Chen (ITCS, 2013)

An adaptive macroblock-mean difference based sorting scheme for fast normalized partial distortion search motion estimation. - Hung-Ming Chen; Po-Hung Chen; Cheng-Tso Lin; Jian-Hong Ciou (Comput. Electr. Eng., 2013)

A 3D visualized expert system for maintenance and management of existing building facilities using reliability-based method. - Hung-Ming Chen; Chuan-Chien Hou; Yu-Hsiang Wang (Expert Syst. Appl., 2013)

Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs. - Chao-Hung Lu; Hung-Ming Chen; Chien-Nan Jimmy Liu; Wen-Yu Shih (Integr., 2013)

Escaped Boundary Pins Routing for High-Speed Boards. - Ching-Yu Chin; Chung-Yi Kuan; Tsung-Ying Tsai; Hung-Ming Chen; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A study of row-based area-array I/O design planning in concurrent chip-package design flow. - Ren-Jie Lee; Hung-Ming Chen (ACM Trans. Design Autom. Electr. Syst., 2013)

Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization. - Shih-Ying Sean Liu; Wan-Ting Lo; Chieh-Jui Lee; Hung-Ming Chen (ACM Trans. Design Autom. Electr. Syst., 2013)

Board- and Chip-Aware Package Wire Planning. - Ren-Jie Lee; Hsin-Wu Hsu; Hung-Ming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Routability-driven bump assignment for chip-package co-design. - Meng-Ling Chen; Tu-Hsiung Tsai; Hung-Ming Chen; Shi-Hao Chen (ASP-DAC, 2014)

Cost-effective decap selection for beyond die power integrity. - Yi-En Chen; Tu-Hsiung Tsai; Shi-Hao Chen; Hung-Ming Chen (DATE, 2014)

Memcomputing: The cape of good hope: [Extended special session description]. - Yiyu Shi 001; Hung-Ming Chen (DATE, 2014)

Planning and placing power clamps for effective CDM protection. - Hsin-Chun Lin; Shih-Ying Sean Liu; Hung-Ming Chen (ICCAD, 2014)

Improving power delivery network design by practical methodologies. - Chia-Chi Huang; Chang-Tzu Lin; Wei-Syun Liao; Chieh-Jui Lee; Hung-Ming Chen; Chia-Hsin Lee; Ding-Ming Kwai (ICCD, 2014)

Usability Evaluation of a Cloud Computing Based Context-aware Healthcare System. - Shu-Lin Wang; Mu-Hsing Kuo; Hung-Ming Chen; André Kushniruk; Elizabeth M. Borycki; Yi-Hsiang Hsu (MIE, 2014)

An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. - Shih-Hsin Hsu; Wei-Zen Chen; Jui-Pin Zheng; Sean S.-Y. Liu; Po-Cheng Pan; Hung-Ming Chen (VLSI-DAT, 2014)

Performance Evaluation of Continuity of Care Records (CCRs): Parsing Models in a Mobile Health Management System. - Hung-Ming Chen; Yong-Zan Liou (J. Medical Syst., 2014)

Automatic image segmentation and classification based on direction texton technique for hemolytic anemia in thin blood smears. - Hung-Ming Chen; Ya-Ting Tsao; Shin-Ni Tsai (Mach. Vis. Appl., 2014)

ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips. - Shih-Ying Sean Liu; Chung-Hung Chang; Hung-Ming Chen; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation. - Chun-Kai Wang; Yeh-Chi Chang; Hung-Ming Chen; Ching-Yu Chin (ACM Trans. Design Autom. Electr. Syst., 2014)

Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function. - Shih-Ying Sean Liu; Ren-Guo Luo; Suradeth Aroonsantidecha; Ching-Yu Chin; Hung-Ming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An approach to anchoring and placing high performance custom digital designs. - Shih-Ying Liu; Tung-Chieh Chen; Hung-Ming Chen (ASP-DAC, 2015)

Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability. - Chun-Kai Wang; Chuan-Chia Huang; Shih-Ying Sean Liu; Ching-Yu Chin; Sheng-Te Hu; Wei-Chen Wu; Hung-Ming Chen (ISPD, 2015)

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation. - Po-Cheng Pan; Ching-Yu Chin; Hung-Ming Chen; Tung-Chieh Chen; Chin-Chieh Lee; Jou-Chun Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Placement optimization of cyber-physical digital microfluidic biochips. - Chun-Hao Kuo; Guan-Ruei Lu; Tsung-Yi Ho; Hung-Ming Chen; Shiyan Hu 001 (BioCAS, 2016)

A New Methodology for Noise Sensor Placement Based on Association Rule Mining. - Yu-Hsiang Hung; Sheng-Hsin Fang; Hung-Ming Chen; Shen-Min Chen; Chang-Tzu Lin; Chia-Hsin Lee (ACM Great Lakes Symposium on VLSI, 2016)

Design and evaluation of a cloud-based Mobile Health Information Recommendation system on wireless sensor networks. - Shu-Lin Wang; Young-Long Chen; Alex Mu-Hsing Kuo; Hung-Ming Chen; Yi-Shiang Shiu (Comput. Electr. Eng., 2016)

Using a branch-and-bound and a genetic algorithm for a single-machine total late work scheduling problem. - Chin-Chia Wu; Yunqiang Yin; Wen-Hsiang Wu; Hung-Ming Chen; Shuenn-Ren Cheng (Soft Comput., 2016)

Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. - Wei-Hsun Liao; Chang-Tzu Lin; Sheng-Hsin Fang; Chien-Chia Huang; Hung-Ming Chen; Ding-Ming Kwai; Yung-Fa Chou (ASP-DAC, 2017)

On reliability hardening in cyber-physical digital-microfluidic biochips. - Guan-Ruei Lu; Guan-Ming Huang; Ansuman Banerjee; Bhargab B. Bhattacharya; Tsung-Yi Ho; Hung-Ming Chen (ASP-DAC, 2017)

Designing A Simple Storage Services (S3) Compatible System Based on Ceph Software-Defined Storage System. - Hung-Ming Chen; Ci-Jie Li; Bi-Shun Ke (ICMSSP, 2017)

On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC. - Sheng-Hsin Fang; Chang-Tzu Lin; Wei-Hsun Liao; Chien-Chia Huang; Li-Chin Chen; Hung-Ming Chen; I-Hsuan Lee; Ding-Ming Kwai; Yung-Fa Chou (ISVLSI, 2017)

An analytical placer for heterogeneous FPGAs via rough-placed packing. - Wan-Ning Wu; Chen Chen; Ching-Yu Chin; Chun-Kai Wang; Hung-Ming Chen (VLSI-DAT, 2017)

Using nanoindentation to investigate the temperature cycling of Sn-37Pb solders. - Hua-Chiang Wen; Wu-Ching Chou; Po-Chen Lin; Yeau-Ren Jeng; Chien-Chang Chen; Hung-Ming Chen; Don Son Jiang; Chun-Hu Cheng (Microelectron. Reliab., 2017)

Generation of PUF-Keys on FPGAs by K-means Frequency Clustering. - K. A. Asha; Abhishek Patyal; Hung-Ming Chen (AsianHOST, 2018)

Performance-preserved analog routing methodology via wire load reduction. - Hao-Yu Chi; Hwa-Yi Tseng; Chien-Nan Jimmy Liu; Hung-Ming Chen (ASP-DAC, 2018)

Multi-level droplet routing in active-matrix based digital-microfluidic biochips. - Guan-Ruei Lu; Bhargab B. Bhattacharya; Tsung-Yi Ho; Hung-Ming Chen (ASP-DAC, 2018)

Analog placement with current flow and symmetry constraints using PCP-SP. - Abhishek Patyal; Po-Cheng Pan; K. A. Asha; Hung-Ming Chen; Hao-Yu Chi; Chien-Nan Liu (DAC, 2018)

Extending ML-OARSMT to net open locator with efficient and effective boolean operations. - Bing-Hui Jiang; Hung-Ming Chen (ICCAD, 2018)

A mutual authentication scheme with user anonymity for cyber-physical and internet of things. - Yung-Feng Lu; Chin-Fu Kuo; Hung-Ming Chen; Guan-Bo Wang; Shih-Chun Chou (RACS, 2018)

On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts. - Po-Cheng Pan; Hung-Wen Huang; Chien-Chia Huang; Abhishek Patyal; Hung-Ming Chen; Tsun-Yu Yang (SMACD, 2018)

A learning-based methodology for routability prediction in placement. - Li-Chin Chen; Chien-Chia Huang; Yao-Lin Chang; Hung-Ming Chen (VLSI-DAT, 2018)

A Multi-Fidelity Model Approach for Simultaneous Scheduling of Machines and Vehicles in Flexible Manufacturing Systems. - James T. Lin; Chun-Chih Chiu; Edward Huang; Hung-Ming Chen (Asia Pac. J. Oper. Res., 2018)

Reliability Hardening Mechanisms in Cyber-Physical Digital-Microfluidic Biochips. - Guan-Ruei Lu; Ansuman Banerjee; Bhargab B. Bhattacharya; Tsung-Yi Ho; Hung-Ming Chen (ACM J. Emerg. Technol. Comput. Syst., 2018)

Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic Biochips. - Guan-Ruei Lu; Chun-Hao Kuo; Kuen-Cheng Chiang; Ansuman Banerjee; Bhargab B. Bhattacharya; Tsung-Yi Ho; Hung-Ming Chen (ACM Trans. Design Autom. Electr. Syst., 2018)

An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis. - Po-Cheng Pan; Chien-Chia Huang; Hung-Ming Chen (DAC, 2019)

Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines. - Hao-Yu Chi; Zi-Jun Lin; Chia-Hao Hung; Chien-Nan Jimmy Liu; Hung-Ming Chen (ICCAD, 2019)

More Effective Power Network Prototyping by Analytical and Centroid Learning. - Yu-Hsiang Chuang; Chang-Tzu Lin; Hung-Ming Chen; Chi-Han Lee; Ting-Sheng Chen (ISCAS, 2019)

Container-based load balancing for WebRTC applications. - Yung-Feng Lu; Hung-Ming Chen; Chin-Fu Kuo; Bo-Kai Tseng; Shih-Chun Chou (RACS, 2019)

A Structure-Based Methodology for Analog Layout Generation. - Yu-Hsien Chen; Hao-Yu Chi; Ling-Yen Song; Chien-Nan Jimmy Liu; Hung-Ming Chen (SMACD, 2019)

Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips. - Jian-De Li; Chun-Hao Kuo; Guan-Ruei Lu; Sying-Jyan Wang; Katherine Shu-Min Li; Tsung-Yi Ho; Hung-Ming Chen; Shiyan Hu 001 (Microelectron. J., 2019)

Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization. - Abhishek Patyal; Hung-Ming Chen; Mark Po-Hung Lin (DAC, 2020)

On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages. - Jyun-Ru Jiang; Yun-Chih Kuo; Simon Yi-Hung Chen; Hung-Ming Chen (DATE, 2020)

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. - Hung-Ming Chen; Chia-Lin Hu; Kang-Yu Chang; Alexandra Küster; Yu-Hsien Lin; Po-Shen Kuo; Wei-Tung Chao; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ICCAD, 2020)

Achieving Analog Layout Integrity through Learning and Migration Invited Talk. - Mark Po-Hung Lin; Hao-Yu Chi; Abhishek Patyal; Zheng-Yao Liu; Jun-Jie Zhao; Chien-Nan Jimmy Liu; Hung-Ming Chen (ICCAD, 2020)

Timing Driven Partition for Multi-FPGA Systems with TDM Awareness. - Sin-Hong Liou; Sean S.-Y. Liu; Richard Sun; Hung-Ming Chen (ISPD, 2020)

Enhanced Privacy with Blockchain-based Storage for Data Sharing. - Yung-Feng Lu; Hung-Ming Chen; Chin-Fu Kuo; Bo-Ting Chen; Zong-Yan Dai (RACS, 2020)

A Three-Factor Mutual Authentication Scheme for Cyber-Physical Systems. - Yung-Feng Lu; Chin-Fu Kuo; Hung-Ming Chen; Hsueh-Wen Tseng; Shih-Chun Chou; Yu-Ming Liao (RACS, 2020)

Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. - Po-Tsang Huang; Tzung-Han Tsai; Po-Jen Yang; Wei Hwang; Hung-Ming Chen (SoCC, 2020)

Understanding user acceptance of blockchain-based smart locker. - Jiunn-Woei Lian; Chih-Teng Chen; Li-Fang Shen; Hung-Ming Chen (Electron. Libr., 2020)

Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP. - Abhishek Patyal; Po-Cheng Pan; K. A. Asha; Hung-Ming Chen; Wei-Zen Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Wire Load Oriented Analog Routing with Matching Constraints. - Hao-Yu Chi; Chien-Nan Jimmy Liu; Hung-Ming Chen (ACM Trans. Design Autom. Electr. Syst., 2020)

On Reconfiguring Memory-Centric AI Edge Devices for CIM. - Hung-Ming Chen; Cheng-En Ni; Kang-Yu Chang; Tzu-Chieh Chiang; Shih-Han Chang; Cheng-Yu Chiang; Bo-Cheng Lai; Chien-Nan Liu; Shyh-Jye Jou (ISOCC, 2021)

Learning Based Placement Refinement to Reduce DRC Short Violations. - Ying-Yao Huang; Chang-Tzu Lin; Wei-Lun Liang; Hung-Ming Chen (VLSI-DAT, 2021)

An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks. - Wei Lu; Po-Tsang Huang; Hung-Ming Chen; Wei Hwang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA). - K. A. Asha; Li En Hsu; Abhishek Patyal; Hung-Ming Chen (ACM J. Emerg. Technol. Comput. Syst., 2021)

A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation. - Hao-Yu Chi; Zi-Jun Lin; Chia-Hao Hung; Chien-Nan Jimmy Liu; Hung-Ming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Practical Substrate Design Considering Symmetrical and Shielding Routes. - Hao-Yu Chi; Simon Yi-Hung Chen; Hung-Ming Chen; Chien-Nan Liu; Yun-Chih Kuo; Ya-Hsin Chang; Kuan-Hsien Ho (DATE, 2022)

DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. - Bo-Cheng Lai; Tzu-Chieh Chiang; Po-Shen Kuo; Wan-Ching Wang; Yan-Lin Hung; Hung-Ming Chen; Chien-Nan Liu; Shyh-Jye Jou (DATE, 2022)

Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator. - Jui-I Kao; Wei Lu; Po-Tsang Huang; Hung-Ming Chen (ISOCC, 2022)

Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. - Wei Lu; Pei-Yu Ge; Po-Tsang Huang; Hung-Ming Chen; Wei Hwang (ISOCC, 2022)

Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks. - Yun-Ru Yang; Wei Lu; Po-Tsang Huang; Hung-Ming Chen (MCSoC, 2022)

An OpenDDS cross-platform data exchange module for cloud-edge-based industrial internet of things. - Hung-Ming Chen; Yung-Feng Lu; Jia-Hong Jhang; Hong-Sheng Sun (RACS, 2022)

Red-black tree I/O management of solid state disk with elastic striping design. - Yung-Feng Lu; Hung-Ming Chen; Chang-Wei Chen; Hsueh-Wen Tseng; Chin-Fu Kuo (RACS, 2022)

On Optimizing Capacitor Array Design for Advanced Node SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Kang-Yu Chang; Mark Po-Hung Lin; Shyh-Jye Jou; Hung-Yu Chen; Chien-Nan Jimmy Liu; Hung-Ming Chen (SMACD, 2022)

Substrate Signal Routing Solution Exploration for High-Density Packages with Machine Learning. - Yeu-Haw Yeh; Simon Yi-Hung Chen; Hung-Ming Chen; Deng-Yao Tu; Guan-Qi Fang; Yun-Chih Kuo; Po-Yang Chen (VLSI-DAT, 2022)

An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. - Jie Zhang; Wei Lu; Po-Tsang Huang; Sih-Han Li; Tsung-Yi Hung; Shih-Hsien Wu; Ming-Ji Dai; I-Shan Chung; Wen-Chao Chen; Chin-Hung Wang; Shyh-Shyuan Sheu; Hung-Ming Chen; et al. (VLSI Technology and Circuits, 2022)

Innovative service model of information services based on the sustainability balanced scorecard: Applied integration of the fuzzy Delphi method, Kano model, and TRIZ. - Hung-Ming Chen; Hung-Yi Wu; Pih-Shuw Chen (Expert Syst. Appl., 2022)

Deep Learning Model for Dynamic Hand Gesture Recognition for Natural Human-Machine Interface on End Devices. - Tsui-Ping Chang; Hung-Ming Chen; Shih-Ying Chen; Wei-Cheng Lin (Int. J. Inf. Syst. Model. Des., 2022)

On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Mark Po-Hung Lin; Yu-Szu Chung; Shyh-Jye Jou; Jieh-Tsorng Wu; Shiuh-Hua Wood Chiang; Chien-Nan Jimmy Liu; Hung-Ming Chen (ASP-DAC, 2023)

DPRoute: Deep Learning Framework for Package Routing. - Yeu-Haw Yeh; Simon Yi-Hung Chen; Hung-Ming Chen; Deng-Yao Tu; Guan-Qi Fang; Yun-Chih Kuo; Po-Yang Chen (ASP-DAC, 2023)

Reshaping System Design in 3D Integration: Perspectives and Challenges. - Hung-Ming Chen; Chu-Wen Ho; Shih-Hsien Wu; Wei Lu; Po-Tsang Huang; Hao-Ju Chang; Chien-Nan Jimmy Liu (ISPD, 2023)

On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC. - Po-Yang Chen; Chang-Yun Liu; Hung-Ming Chen; Po-Tsang Huang (ISQED, 2023)

Layout Synthesis of Analog Primitive Cells with Variational Autoencoder. - Po-Chun Wang; Mark Po-Hung Lin; Chien-Nan Jimmy Liu; Hung-Ming Chen (SMACD, 2023)

Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings. - Abhishek Patyal; Hung-Ming Chen; Mark Po-Hung Lin; Guan-Qi Fang; Simon Yi-Hung Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

On Reducing LDE Variations in Modern Analog Placement. - A. K. Thasreefa; Abhishek Patyal; Hao-Yu Chi; Mark Po-Hung Lin; Hung-Ming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block. - Cheng-Chen Lin; Wei Lu; Po-Tsang Huang; Hung-Ming Chen (AICAS, 2024)

CFIRSTNET: Comprehensive Features for Static IR Drop Estimation with Neural Network. - Yu-Tung Liu; Yu-Hao Cheng; Shao-Yu Wu; Hung-Ming Chen (ICCAD, 2024)

A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning. - Wei Lu; Han-Hsiang Pei; Jheng-Rong Yu; Hung-Ming Chen; Po-Tsang Huang (ISCAS, 2024)

Design of A Traffic Control Mechanism Based on O-RAN. - Hung-Ming Chen; Yung-Feng Lu; Guan-Bo Fang; Chin-Chien Lu (ISPACS, 2024)

Designing Dynamic Access Control Based on ZTA in A 5G MANO System. - Hung-Ming Chen; Yung-Feng Lu; Yu-Lung Kuo; Yi-Ming Chuang (ISPACS, 2024)

Enabling System Design in 3D Integration: Technologies and Methodologies. - Hung-Ming Chen (ISPD, 2024)

Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization. - Bo-Han Li; Kuan-Chih Lin; Hao Zuo; Po-Cheng Pan; Hung-Ming Chen; Shyh-Jye Jou; Chien-Nan Jimmy Liu; Bo-Cheng Lai (MWSCAS, 2024)

ML/DL-Based Signal Integrity Optimization for InFO Routing. - Bo-Kai Kang; Hao-Ju Chang; Hung-Ming Chen; Chien-Nan Jimmy Liu (NewCAS, 2024)

Mitigating Power and Process Variation for Analog CIM Design Migration. - Shih-Han Chang; Shih-Yu Chen; Chun-Wen Yang; Hau-Wei Huang; Yu-Cheng Yang; Wei-Liang Chen; Chien-Nan Liu; Hung-Ming Chen (SMACD, 2024)

Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. - Wei Lu; Jie Zhang; Yi-Hui Wei; Hsu-Ming Hsiao; Sih-Han Li; Chao-Kai Hsu; Chih-Cheng Hsiao; Feng-Hsiang Lo; Shyh-Shyuan Sheu; Chin-Hung Wang; Wei-Chung Lo; Shih-Chieh Chang; et al. (VLSI Technology and Circuits, 2024)

3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi. - Bo-Jheng Shih; Yu-Ming Pan; Hao-Tung Chung; Chieh-Ling Lee; I-Chun Hsieh; Nein-Chih Lin; Chih-Chao Yang; Po-Tsang Huang; Hung-Ming Chen; Chiao-Yen Wang; Huan-Yu Chiu; Huang-Chung Cheng; et al. (VLSI Technology and Circuits, 2024)

One Raman DTS Interrogator Channel Supports a Dual Separate Path to Realize Spatial Duplexing. - Cheng-Kai Yao 001; Chun-Hsiang Peng; Hung-Ming Chen; Wen-Yang Hsu; Tzu-Chiao Lin; Yibeltal Chanie Manie; Peng-Chun Peng (Sensors, 2024)

On Awareness of Offset-Via and Teardrop in Advanced Packaging Interconnect Synthesis. - Hao-Ju Chang; Yu-Hung Chen; Hao-Wei Huang; Yihua Yeh; Hung-Ming Chen; Chien-Nan Jimmy Liu (ASP-DAC, 2025)

Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization. - Cheng-Yu Chiang; Yi-Hsien Chiang; Chao-Chi Lan; Yang Hsu; Che-Ming Chang; Shao-Chi Huang; Sheng-Hua Wang; Yao-Wen Chang; Hung-Ming Chen (ASP-DAC, 2025)

Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout Synthesis. - Siou-Sian Lin; Shih-Yu Chen; Yu-Ping Huang; Tzu-Chuan Lin; Hung-Ming Chen; Wei-Zen Chen (DATE, 2025)

Irregular Operation-Unit-based Compression for Non-Volatile Computation-in-Memory Accelerator. - Liang-Te Huang; Wei Lu; Hung-Ming Chen; Po-Tsang Huang (ISCAS, 2025)

Efficient Guard Ring-Aware Placement for FinFET Analog Circuits with Diffusion Sharing. - Shih-Yu Chen; Tzu-Hsiang Wei; Haoju Chang; Hung-Ming Chen; Chien-Nan Jimmy Liu (SMACD, 2025)

GIRD: A Green IR-Drop Estimation Method. - Chee-An Yu; Yu-Tung Liu; Yu-Hao Cheng; Shao-Yu Wu; Hung-Ming Chen; C.-C. Jay Kuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)