A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI. - James B. Kuo; Hung-Pin Chen 001; H. J. Huang (ISCAS, 1993)

On Testing Wave Pipelined Circuits. - Jui-Ching Shyur; Hung-Pin Chen 001; Tai-Ming Parng (DAC, 1994)

A new approach of multi-stage fuzzy logic inference. - Hung-Pin Chen 001; Tai-Ming Parng (Fuzzy Sets Syst., 1996)

A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI. - Hung-Pin Chen 001; James B. Kuo (ICECS, 2004)