A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS. - Kang-Wei Hsueh; Yu-Kai Chou; Yu-Hsuan Tu; Yi-Fu Chen; Ya-Lun Yang; Hung-Sung Li (ISSCC, 2008)

A multi-format Blu-ray player SoC in 90nm CMOS. - Chi-Cheng Ju; Tsu-Ming Liu; Chih-Chieh Yang; Shih-Hung Lin; Kuo-Pin Lan; Chien-Hua Wu; Ting-Hsun Wei; Chi-Chin Lien; Jiun-Yuan Wu; Chih-Hao Hsiao; Te-Wei Chen; Yeh-Lin Chu; et al. (ISSCC, 2009)

A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer. - Yan-Bin Luo; Ping Chen; Qui-Ting Chen; Chih-Yong Wang; Chan-Hao Chang; Szu-Jui Fu; Chien-Ming Chen; Hung-Sung Li (ISSCC, 2009)

A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching. - Yung-Hui Chung; Meng-Hsuan Wu; Hung-Sung Li (CICC, 2013)

A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS. - Jie-Wei Lai; Chi-Hsueh Wang; Kaipon Kao; Anson Lin; Yi-Hsien Cho; Lan-chou Cho; Meng-Hsiung Hung; Xin-Yu Shih; Che-Min Lin; Sheng-Hong Yan; Yuan-Hung Chung; Paul C. P. Liang; et al. (ISSCC, 2013)

A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS. - Yung-Hui Chung; Meng-Hsuan Wu; Hung-Sung Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)