A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS. - Hung-Yen Tai; Hung-Wei Chen; Hsin-Shu Chen (VLSIC, 2012)

A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS. - Yao-Sheng Hu; Chi-Huai Shih; Hung-Yen Tai; Hung-Wei Chen; Hsin-Shu Chen (A-SSCC, 2014)

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. - Hung-Yen Tai; Yao-Sheng Hu; Hung-Wei Chen; Hsin-Shu Chen (ISSCC, 2014)

A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS. - Hung-Yen Tai; Cheng-Hsueh Tsai; Pao-Yang Tsai; Hung-Wei Chen; Hsin-Shu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An 8-bit 900MS/S two-step SAR ADC. - Po-Chao Huang; Yao-Sheng Hu; Hung-Yen Tai; Hsin-Shu Chen (ISCAS, 2016)

A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC. - Yao-Sheng Hu; Po-Chao Huang; Hung-Yen Tai; Hsin-Shu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique. - Tsung-Han Tsai; Hung-Yen Tai; Pao-Yang Tsai; Cheng-Hsueh Tsai; Hsin-Shu Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration. - Hsin-Shu Chen; Sheng-Hsiang Huang; Hung-Yen Tai; Sen-Wei Lin; Shih-Wei Wu (ISCAS, 2020)