A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < -61dB at 2.8 GS/s With DEMDRZ Technique. - Wei-Te Lin; Hung-Yi Huang; Tai-Haur Kuo (IEEE J. Solid State Circuits, 2014)

A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation. - Hung-Yi Huang; Tai-Haur Kuo (VLSI Circuits, 2019)

23.5 A 0.41mA Quiescent Current, 0.00091% THD+N Class-D Audio Amplifier with Frequency Equalization for PWM-Residual-Aliasing Reduction. - Shih-Hsiung Chien; Tai-Haur Kuo; Hung-Yi Huang; Hong-Bin Wang; Yi-Zhi Qiu (ISSCC, 2020)

A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < -77dBc IM3. - Hung-Yi Huang; Xin-Yu Chen; Tai-Haur Kuo (VLSI Circuits, 2020)

A 0.07-mm2 162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing. - Hung-Yi Huang; Tai-Haur Kuo (IEEE J. Solid State Circuits, 2020)

A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone. - Hung-Yi Huang; Xin-Yu Chen; Tai-Haur Kuo (IEEE J. Solid State Circuits, 2021)

A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm. - Wei-Hsin Tseng; Willy Lin; Chung-Wei Hsu; Chang-Yang Huang; Yu-Sian Lin; Hung-Yi Huang; HsinWei Chen; Sheng-Hui Liao; Kuan-Dar Chen; Jon Strange; Gabriele Manganaro (ISSCC, 2023)

The human-centric framework integrating knowledge distillation architecture with fine-tuning mechanism for equipment health monitoring. - Jr-Fong Dang; Tzu-Li Chen; Hung-Yi Huang (Adv. Eng. Informatics, 2025)