A Fast and Accurate Gate-Level Transient Fault Simulation Environment. - Hungse Cha; Elizabeth M. Rudnick; Gwan S. Choi; Janak H. Patel; Ravishankar K. Iyer (FTCS, 1993)

A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. - Hungse Cha; Janak H. Patel (ICCD, 1993)

Fast timing simulation of transient faults in digital circuits. - Abhijit Dharchoudhury; Sung-Mo Kang; Hungse Cha; Janak H. Patel (ICCAD, 1994)

Latch Design for Transient Pulse Tolerance. - Hungse Cha; Janak H. Patel (ICCD, 1994)

A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. - Hungse Cha; Elizabeth M. Rudnick; Janak H. Patel; Ravishankar K. Iyer; Gwan S. Choi (IEEE Trans. Computers, 1996)