Fast Smith-Waterman hardware implementation. - Zubair Nawaz; Koen Bertels; Huseyin Ekin Sumbul (IPDPS Workshops, 2010)

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. - Qiuling Zhu; Berkin Akin; Huseyin Ekin Sumbul; Fazle Sadi; James C. Hoe; Larry T. Pileggi; Franz Franchetti (3DIC, 2013)

Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware. - Qiuling Zhu; Tobias Graf; Huseyin Ekin Sumbul; Larry T. Pileggi; Franz Franchetti (HPEC, 2013)

Building trusted ICs using split fabrication. - Kaushik Vaidyanathan; Bishnu Prasad Das; Huseyin Ekin Sumbul; Renzhi Liu; Larry T. Pileggi (HOST, 2014)

Efficient and secure intellectual property (IP) design with split fabrication. - Kaushik Vaidyanathan; Renzhi Liu; Huseyin Ekin Sumbul; Qiuling Zhu; Franz Franchetti; Larry T. Pileggi (HOST, 2014)

A synthesis methodology for application-specific logic-in-memory designs. - Huseyin Ekin Sumbul; Kaushik Vaidyanathan; Qiuling Zhu; Franz Franchetti; Larry T. Pileggi (DAC, 2015)

A Novel Design Methodology for Synthesizing Application-Specific Logic-in-Memory Blocks. - Huseyin Ekin Sumbul (2015)

A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS. - Gregory K. Chen; Raghavan Kumar; Huseyin Ekin Sumbul; Phil C. Knag; Ram K. Krishnamurthy (VLSI Circuits, 2018)

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Sergey Gribok; et al. (FCCM, 2019)

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. - Eriko Nurvitadhi; Dongup Kwon; Ali Jafari; Andrew Boutros; Jaewoong Sim; Phillip Tomson; Huseyin Sumbul; Gregory K. Chen; Phil C. Knag; Raghavan Kumar; Ram Krishnamurthy 001; Debbie Marr; et al. (FPGA, 2019)

A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. - Gregory K. Chen; Raghavan Kumar; Huseyin Ekin Sumbul; Phil C. Knag; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2019)

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. - Amit Agarwal 001; Steven Hsu; Simeon Realov; Mark A. Anders 001; Gregory K. Chen; Monodeep Kar; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Himanshu Kaul; Sanu Mathew; Mahesh Kumashikar; et al. (ISSCC, 2020)

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. - Mark A. Anders 001; Himanshu Kaul; Seongjong Kim; Gregory K. Chen; Raghavan Kumar; Huseyin Ekin Sumbul; Phil C. Knag; Monodeep Kar; Steven K. Hsu; Amit Agarwal 001; Vikram B. Suresh; Sanu K. Mathew; et al. (ISSCC, 2020)

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. - Steven Hsu; Amit Agarwal 001; Simeon Realov; Mark A. Anders 001; Gregory K. Chen; Monodeep Kar; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Himanshu Kaul; Vikram B. Suresh; Sanu Mathew; et al. (VLSI Circuits, 2020)

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. - Monodeep Kar; Amit Agarwal 001; Steven Hsu; David Moloney; Gregory K. Chen; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Mark A. Anders 001; Himanshu Kaul; Jonathan Byrne; Luca Sarti; et al. (VLSI Circuits, 2020)

A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. - Phil C. Knag; Gregory K. Chen; Huseyin Ekin Sumbul; Raghavan Kumar; Mark A. Anders 001; Himanshu Kaul; Steven K. Hsu; Amit Agarwal 001; Monodeep Kar; Seongjong Kim; Ram K. Krishnamurthy (VLSI Circuits, 2020)

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. - Phil C. Knag; Gregory K. Chen; Huseyin Ekin Sumbul; Raghavan Kumar; Steven K. Hsu; Amit Agarwal 001; Monodeep Kar; Seongjong Kim; Mark A. Anders 001; Himanshu Kaul; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2021)

System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars. - Huseyin Ekin Sumbul; Tony F. Wu; Yuecheng Li; Syed Shakib Sarwar; William Koven; Eli Murphy-Trotzky; Xingxing Cai; Elnaz Ansari; Daniel H. Morris; Huichu Liu; Doyun Kim; Edith Beigné (CICC, 2022)

A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. - Linyan Mei; Huichu Liu; Tony F. Wu; Huseyin Ekin Sumbul; Marian Verhelst; Edith Beigné (DATE, 2022)

Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications. - Daniel H. Morris; Huichu Liu; Tony F. Wu; Huseyin Ekin Sumbul; Elnaz Ansari; Alexandre Barachant; Jonathan Reid; Edith Beigné (VLSI Technology and Circuits, 2022)

Power-of-Two Quantization for Low Bitwidth and Hardware Compliant Neural Networks. - Dominika Przewlocka-Rus; Syed Shakib Sarwar; Huseyin Ekin Sumbul; Yuecheng Li; Barbara De Salvo (CoRR, 2022)

DRESS: Dynamic REal-time Sparse Subnets. - Zhongnan Qu; Syed Shakib Sarwar; Xin Dong 009; Yuecheng Li; Huseyin Ekin Sumbul; Barbara De Salvo (CoRR, 2022)

A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. - Matheus Trevisan Moreira; William Koven; Tony F. Wu; Huseyin Ekin Sumbul; Edith Beigné (ASYNC, 2023)

11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. - Tony F. Wu; Huichu Liu; Huseyin Ekin Sumbul; Lita Yang; Dipti Baheti; Jeremy Coriell; William Koven; Anu Krishnan; Mohit Mittal; Matheus Trevisan Moreira; Max Waugaman; Laurent Ye; et al. (ISSCC, 2024)

Characterization and Design of 3D-Stacked Memory for Image Signal Processing on AR/VR Devices. - Lita Yang; Changjung Kao; Sriseshan Srikanth; Huseyin Ekin Sumbul; Tony F. Wu; Huichu Liu; Edith Beigné (MEMSYS, 2024)

A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. - Huseyin Ekin Sumbul; Jae-sun Seo; Daniel H. Morris; Edith Beigné (IEEE Micro, 2024)

A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint. - Huseyin Ekin Sumbul; Arne Symons; Lita Yang; Huichu Liu; Tony F. Wu; Matheus Trevisan Moreira; Debabrata Mohapatra; Abhinav Agarwal; Kaushik Ravindran; Chris Thompson; Yuecheng Li; Edith Beigné (DATE, 2025)

Re-CATA: Real-Time and Flexible Accelerator Design Framework for On-Device Codec Avatars. - Yongan Zhang; Yuecheng Li; Syed Shakib Sarwar; Huseyin Ekin Sumbul; Yonggan Fu; Haoran You; Cheng Wan 005; Yingyan Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)