A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures. - Hussain Al-Asaad; Elias S. Manolakos (DFT, 1993)

Concurrent error correction in iterative circuits by recomputing with partitioning and voting. - Hussain Al-Asaad; Edward C. Czeck (VTS, 1993)

Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths. - Hussain Al-Asaad; Mankuan Michael Vai; James Feldman (ICCD, 1994)

Design verification via simulation and automatic test pattern generation. - Hussain Al-Asaad; John P. Hayes (ICCAD, 1995)

Online BIST for Embedded Systems. - Hussain Al-Asaad; Brian T. Murray; John P. Hayes (IEEE Des. Test Comput., 1998)

Scalable Test Generators for High-Speed Datapath Circuits. - Hussain Al-Asaad; John P. Hayes; Brian T. Murray (J. Electron. Test., 1998)

High-level design verification of microprocessors via error modeling. - David Van Campenhout; Hussain Al-Asaad; John P. Hayes; Trevor N. Mudge; Richard B. Brown (ACM Trans. Design Autom. Electr. Syst., 1998)

Lifetime validation of digital systems via fault modeling and test generation. - Hussain Al-Asaad (1998)

ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. - Hussain Al-Asaad; John P. Hayes (VTS, 2000)

Logic Design Validation via Simulation and Automatic Test Pattern Generation. - Hussain Al-Asaad; John P. Hayes (J. Electron. Test., 2000)

Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling. - Hussain Al-Asaad; Alireza Sarvi (VLSI, 2003)

Approaches for Monitoring Vectors on Microprocessor Buses. - Hector Arteaga; Hussain Al-Asaad (ESA/VLSI, 2004)

Survey and Evaluation of Low-Power Full-Adder Cells. - Ahmed Sayed; Hussain Al-Asaad (ESA/VLSI, 2004)

Mutation-based validation of high-level microprocessor implementations. - Jorge Campos; Hussain Al-Asaad (HLDVT, 2004)

A Novel Functional Testing and Verification Technique for Logic Circuits. - Hussain Al-Asaad; Ganesh Valliappan; Lourdes Ramirez (CDES, 2005)

On Increasing the Observability of Modern Microprocessors. - Hector Arteaga; Hussain Al-Asaad (CDES, 2005)

MVP: a mutation-based validation paradigm. - Jorge Campos; Hussain Al-Asaad (HLDVT, 2005)

EGFC: An exact global fault collapsing tool for combinational circuits. - Hussain Al-Asaad (Circuits, Signals, and Systems, 2005)

Search-Space Optimizations for High-Level ATPG. - Jorge Campos; Hussain Al-Asaad (MTV, 2005)

Survey and Evaluation of Low-Power Flip-Flops. - Ahmed Sayed; Hussain Al-Asaad (CDES, 2006)

Circuit Profiling Mechanisms for High-Level {ATPG}. - Jorge Campos; Hussain Al-Asaad (MTV, 2006)

Efficient Global Fault Collapsing for Combinational Library Modules. - Hussain Al-Asaad (CDES, 2007)

A New Statistical Approach for Glitch Estimation in Combinational Circuits. - Ahmed Sayed; Hussain Al-Asaad (ISCAS, 2007)

A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions. - Jorge Campos; Hussain Al-Asaad (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling. - Hussain Al-Asaad (CDES, 2009)

Low Power Methodologies and Challenges for PWM DC-DC Converters. - Calvin Chiem; Hussain Al-Asaad (CDES, 2009)

Time-Redundant Logic-Level Protection Mechanisms from Soft Errors in Digital Systems. - Hussain Al-Asaad (CDES, 2010)

A Comparison of NMOS to PMOS Starved Buffer Implementations for the Delay Line in a PWM DC-DC Converters. - Calvin Chiem; Hussain Al-Asaad (CDES, 2010)

Efficient techniques for reducing error latency in on-line periodic built-in self-test. - Hussain Al-Asaad (IEEE Instrum. Meas. Mag., 2010)

A Brief Survey of Fault Tolerant Techniques for Field Programmable Gate Arrays. - Raihana Yarzada; Divya Singh; Hussain Al-Asaad (CCWC, 2022)

Advancements in Secure Computing: Exploring Automated Repair Debugging and Verification Techniques for Hardware Design. - Alireza Abolhasani Zeraatkar; Parnian Shabani Kamran; Hussain Al-Asaad (CCWC, 2024)

On the Performance of Malware Detection Classifiers Using Hardware Performance Counters. - Alireza Abolhasani Zeraatkar; Parnian Shabani Kamran; Inderpreet Kaur; Nagabindu Ramu; Tyler Sheaves; Hussain Al-Asaad (SmartNets, 2024)

Survey of Verification of RISC-V Processors. - Chloe Tain; Savita Patil; Hussain Al-Asaad (J. Electron. Test., 2025)