8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. - Huy Cu Ngo; Kengo Nakata; Toru Yoshioka; Yuki Terashima; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2017)

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. - Bangan Liu; Huy Cu Ngo; Kengo Nakata; Wei Deng 001; Yuncheng Zhang; Junjun Qiu; Toru Yoshioka; Jun Emmei; Haosheng Zhang; Jian Pang; Aravind Tharayil Narayanan; Dongsheng Yang 002; et al. (CICC, 2018)

A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. - Hanli Liu; Dexian Tang; Zheng Sun 001; Wei Deng 001; Huy Cu Ngo; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications. - Hanli Liu; Dexian Tang; Zheng Sun 001; Wei Deng 001; Huy Cu Ngo; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2018)

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Huy Cu Ngo; Wei Deng 001; Kengo Nakata; Toru Yoshioka; Jun Emmei; Jian Pang; Aravind Tharayil Narayanan; Haosheng Zhang; Teruki Someya; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR. - Fumihiko Tachibana; Huy Cu Ngo; Go Urakawa; Takashi Toi; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Junji Wadatsumi; Hiroyuki Kobayashi; Jun Deguchi (ESSCIRC, 2022)

A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver. - Fumihiko Tachibana; Huy Cu Ngo; Go Urakawa; Takashi Toi; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Junji Wadatsumi; Hiroyuki Kobayashi; Jun Deguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)